mirror of https://github.com/openXC7/prjxray.git
Refactor Configuration::InitWithPackets template method
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
7bc54d0c56
commit
d91b0a5006
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@ -65,12 +65,11 @@ class Configuration {
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FrameMap frames_;
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};
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template <>
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template <typename ArchType>
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template <typename Collection>
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absl::optional<Configuration<Series7>> Configuration<Series7>::InitWithPackets(
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const typename Series7::Part& part,
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Collection& packets) {
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using ArchType = Series7;
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absl::optional<Configuration<ArchType>>
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Configuration<ArchType>::InitWithPackets(const typename ArchType::Part& part,
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Collection& packets) {
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// Registers that can be directly written to.
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uint32_t command_register = 0;
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uint32_t frame_address_register = 0;
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@ -154,8 +153,9 @@ absl::optional<Configuration<Series7>> Configuration<Series7>::InitWithPackets(
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start_new_write = false;
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}
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// 7-series frames are 101-words long. Writes
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// to this register can be multiples of that to
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// Number of words in configuration frames
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// depend on tje architecture. Writes to this
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// register can be multiples of that number to
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// do auto-incrementing block writes.
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for (size_t ii = 0; ii < packet.data().size();
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ii += ArchType::words_per_frame) {
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@ -196,269 +196,6 @@ absl::optional<Configuration<Series7>> Configuration<Series7>::InitWithPackets(
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return Configuration(part, frames);
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}
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template <>
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template <typename Collection>
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absl::optional<Configuration<UltraScale>>
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Configuration<UltraScale>::InitWithPackets(
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const typename UltraScale::Part& part,
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Collection& packets) {
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using ArchType = UltraScale;
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// Registers that can be directly written to.
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uint32_t command_register = 0;
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uint32_t frame_address_register = 0;
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uint32_t mask_register = 0;
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uint32_t ctl1_register = 0;
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// Internal state machine for writes.
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bool start_new_write = false;
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typename ArchType::FrameAddress current_frame_address = 0;
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Configuration<ArchType>::FrameMap frames;
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for (auto packet : packets) {
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if (packet.opcode() !=
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ConfigurationPacket<
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typename ArchType::ConfRegType>::Opcode::Write) {
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continue;
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}
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switch (packet.address()) {
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case ArchType::ConfRegType::MASK:
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if (packet.data().size() < 1)
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continue;
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mask_register = packet.data()[0];
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break;
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case ArchType::ConfRegType::CTL1:
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if (packet.data().size() < 1)
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continue;
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ctl1_register =
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packet.data()[0] & mask_register;
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break;
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case ArchType::ConfRegType::CMD:
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if (packet.data().size() < 1)
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continue;
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command_register = packet.data()[0];
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// Writes to CMD trigger an immediate action. In
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// the case of WCFG, that is just setting a flag
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// for the next FDIR.
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if (command_register == 0x1) {
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start_new_write = true;
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}
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break;
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case ArchType::ConfRegType::IDCODE:
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// This really should be a one-word write.
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if (packet.data().size() < 1)
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continue;
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// If the IDCODE doesn't match our expected
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// part, consider the bitstream invalid.
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if (packet.data()[0] != part.idcode()) {
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return {};
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}
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break;
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case ArchType::ConfRegType::FAR:
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// This really should be a one-word write.
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if (packet.data().size() < 1)
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continue;
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frame_address_register = packet.data()[0];
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// Per UG470, the command present in the CMD
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// register is executed each time the FAR
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// register is laoded with a new value. As we
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// only care about WCFG commands, just check
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// that here. CTRL1 is completely undocumented
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// but looking at generated bitstreams, bit 21
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// is used when per-frame CRC is enabled.
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// Setting this bit seems to inhibit the
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// re-execution of CMD during a FAR write. In
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// practice, this is used so FAR writes can be
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// added in the bitstream to show progress
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// markers without impacting the actual write
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// operation.
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if (bit_field_get(ctl1_register, 21, 21) == 0 &&
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command_register == 0x1) {
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start_new_write = true;
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}
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break;
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case ArchType::ConfRegType::FDRI: {
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if (start_new_write) {
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current_frame_address =
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frame_address_register;
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start_new_write = false;
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}
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// UltraScale frames are 123-words long. Writes
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// to this register can be multiples of that to
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// do auto-incrementing block writes.
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for (size_t ii = 0; ii < packet.data().size();
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ii += ArchType::words_per_frame) {
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frames[current_frame_address] =
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packet.data().subspan(
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ii, ArchType::words_per_frame);
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auto next_address =
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part.GetNextFrameAddress(
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current_frame_address);
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if (!next_address)
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break;
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// Bitstreams appear to have 2 frames of
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// padding between rows.
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if (next_address &&
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(next_address->block_type() !=
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current_frame_address
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.block_type() ||
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next_address
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->is_bottom_half_rows() !=
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current_frame_address
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.is_bottom_half_rows() ||
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next_address->row() !=
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current_frame_address.row())) {
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ii += 2 *
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ArchType::words_per_frame;
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}
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current_frame_address = *next_address;
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}
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break;
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}
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default:
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break;
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}
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}
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return Configuration(part, frames);
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}
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template <>
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template <typename Collection>
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absl::optional<Configuration<UltraScalePlus>>
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Configuration<UltraScalePlus>::InitWithPackets(
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const typename UltraScale::Part& part,
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Collection& packets) {
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using ArchType = UltraScalePlus;
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// Registers that can be directly written to.
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uint32_t command_register = 0;
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uint32_t frame_address_register = 0;
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uint32_t mask_register = 0;
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uint32_t ctl1_register = 0;
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// Internal state machine for writes.
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bool start_new_write = false;
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typename ArchType::FrameAddress current_frame_address = 0;
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Configuration<ArchType>::FrameMap frames;
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for (auto packet : packets) {
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if (packet.opcode() !=
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ConfigurationPacket<
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typename ArchType::ConfRegType>::Opcode::Write) {
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continue;
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}
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switch (packet.address()) {
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case ArchType::ConfRegType::MASK:
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if (packet.data().size() < 1)
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continue;
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mask_register = packet.data()[0];
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break;
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case ArchType::ConfRegType::CTL1:
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if (packet.data().size() < 1)
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continue;
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ctl1_register =
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packet.data()[0] & mask_register;
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break;
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case ArchType::ConfRegType::CMD:
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if (packet.data().size() < 1)
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continue;
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command_register = packet.data()[0];
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// Writes to CMD trigger an immediate action. In
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// the case of WCFG, that is just setting a flag
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// for the next FDIR.
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if (command_register == 0x1) {
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start_new_write = true;
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}
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break;
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case ArchType::ConfRegType::IDCODE:
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// This really should be a one-word write.
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if (packet.data().size() < 1)
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continue;
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// If the IDCODE doesn't match our expected
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// part, consider the bitstream invalid.
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if (packet.data()[0] != part.idcode()) {
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return {};
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}
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break;
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case ArchType::ConfRegType::FAR:
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// This really should be a one-word write.
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if (packet.data().size() < 1)
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continue;
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frame_address_register = packet.data()[0];
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// Per UG470, the command present in the CMD
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// register is executed each time the FAR
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// register is laoded with a new value. As we
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// only care about WCFG commands, just check
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// that here. CTRL1 is completely undocumented
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// but looking at generated bitstreams, bit 21
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// is used when per-frame CRC is enabled.
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// Setting this bit seems to inhibit the
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// re-execution of CMD during a FAR write. In
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// practice, this is used so FAR writes can be
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// added in the bitstream to show progress
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// markers without impacting the actual write
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// operation.
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if (bit_field_get(ctl1_register, 21, 21) == 0 &&
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command_register == 0x1) {
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start_new_write = true;
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}
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break;
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case ArchType::ConfRegType::FDRI: {
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if (start_new_write) {
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current_frame_address =
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frame_address_register;
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start_new_write = false;
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}
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// UltraScale frames are 93-words long. Writes
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// to this register can be multiples of that to
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// do auto-incrementing block writes.
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for (size_t ii = 0; ii < packet.data().size();
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ii += ArchType::words_per_frame) {
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frames[current_frame_address] =
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packet.data().subspan(
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ii, ArchType::words_per_frame);
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auto next_address =
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part.GetNextFrameAddress(
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current_frame_address);
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if (!next_address)
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break;
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// Bitstreams appear to have 2 frames of
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// padding between rows.
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if (next_address &&
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(next_address->block_type() !=
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current_frame_address
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.block_type() ||
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next_address
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->is_bottom_half_rows() !=
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current_frame_address
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.is_bottom_half_rows() ||
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next_address->row() !=
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current_frame_address.row())) {
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ii += 2 *
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ArchType::words_per_frame;
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}
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current_frame_address = *next_address;
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}
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break;
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}
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default:
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break;
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}
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}
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return Configuration(part, frames);
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}
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} // namespace xilinx
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} // namespace prjxray
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