mirror of https://github.com/openXC7/prjxray.git
Expand tilegrid to entire grid.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
parent
b5a1f8a5ea
commit
d6754069bd
|
|
@ -420,9 +420,11 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
|
|||
|
||||
for dst_tile, wordbase in localutil.propagate_up_INT(
|
||||
grid_x, grid_y, database, tiles_by_grid, wordbase):
|
||||
assert 'segment' in dst_tile, (
|
||||
(grid_x, grid_y), dst_tile,
|
||||
tiles_by_grid[(grid_x, grid_y)])
|
||||
if 'segment' not in dst_tile:
|
||||
print('WARNING: Missing segment for {} ({}, {}) {}'.format(
|
||||
tiles_by_grid[(grid_x, grid_y)], grid_x, grid_y,
|
||||
dst_tile))
|
||||
continue
|
||||
|
||||
#verbose and print(' dst_tile', dst_tile)
|
||||
if 'segment' in dst_tile:
|
||||
|
|
@ -468,6 +470,9 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
|
|||
|
||||
# FIXME: PCIE block cuts out some BRAM
|
||||
# this messes up algorithm as is and may cause this to fail
|
||||
if grid_y < 0:
|
||||
continue
|
||||
|
||||
dst_tile_name = tiles_by_grid[(grid_x, grid_y)]
|
||||
|
||||
dst_tile = database[dst_tile_name]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
N ?= 15
|
||||
N ?= 35
|
||||
GENERATE_ARGS?="--oneval KEEPER --dframe 27 --dword 3 --dbit 3"
|
||||
include ../fuzzaddr/common.mk
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ proc run {} {
|
|||
# Mostly doesn't matter since IOB are special, but add anyway
|
||||
create_pblock roi
|
||||
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
|
||||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
|
||||
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI_TILEGRID)"
|
||||
|
||||
loc_pins
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ import os
|
|||
import random
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.db import Database
|
||||
from prjxray import verilog
|
||||
|
||||
|
||||
|
|
@ -17,11 +18,15 @@ def gen_iobs():
|
|||
IOB33: not a diff pair. Relatively rare (at least in ROI...2 of them?)
|
||||
Focus on IOB33S to start
|
||||
'''
|
||||
for _tile_name, site_name, site_type in util.get_roi().gen_sites(
|
||||
# ['IOB33', 'IOB33S']):
|
||||
# FIXME: special cases on IOB33
|
||||
['IOB33S']):
|
||||
yield site_name, site_type
|
||||
db = Database(util.get_db_root())
|
||||
grid = db.grid()
|
||||
for tile_name in grid.tiles():
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
|
||||
for site_name, site_type in gridinfo.sites.items():
|
||||
if site_type in ['IOB33S']:
|
||||
yield site_name, site_type
|
||||
|
||||
|
||||
def write_params(ports):
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@ proc assign_iobs {} {
|
|||
|
||||
proc make_project {} {
|
||||
# Generate .bit only over ROI
|
||||
make_project_roi XRAY_ROI
|
||||
make_project_roi XRAY_ROI_TILEGRID
|
||||
}
|
||||
|
||||
proc make_project_roi { roi_var } {
|
||||
|
|
|
|||
Loading…
Reference in New Issue