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Make n5FFMUX match Vivado GUI. 

CLBLL_L.SLICEL_X0.D5FF.MUX.A -> CLBLL_L.SLICEL_X0.D5FFMUX.IN_A
CLBLL_L.SLICEL_X0.D5FF.MUX.B -> CLBLL_L.SLICEL_X0.D5FFMUX.IN_B

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2018-02-05 17:55:21 -08:00
parent 90ec237f56
commit cf64309ee3
2 changed files with 3 additions and 3 deletions
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4
fuzzers/012-clbn5ffmux/generate.py
View File

@ -26,7 +26,7 @@ for l in f:
# Theory: there is one bit for each mux positon
# In each config 3 muxes are in one position, other 3 are in another
inv = int(i == n)
segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
segmk.addtag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
segmk.addtag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
segmk.compile()
segmk.write()

2
htmlgen/htmlgen.py
View File

@ -212,7 +212,7 @@ for segname, segdata in grid["segments"].items():
print(" loading %s segbits." % segtype)
with db_open("segbits_%s.db" % segtype) as f:
for line in f:
if re.search(r"(\.[ABCD](FF|OUT)MUX\.)|(\.PRECYINIT\.)", line):
if re.search(r"(\.[ABCD](5?FF|OUT)MUX\.)|(\.PRECYINIT\.)", line):
add_pip_bits(line)
else:
add_single_bit(line)