063-gtp-common: add gtp_common fuzzer

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-01-14 16:25:06 +01:00
parent 5c892e4f44
commit ccccd20ed8
6 changed files with 330 additions and 0 deletions

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# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
N ?= 20
include ../fuzzer.mk
database: build/segbits_gtp_common.db
build/segbits_gtp_common.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o build/segbits_gtp_common.rdb $(addsuffix /segdata_gtp_common.txt,$(SPECIMENS))
build/segbits_gtp_common.db: build/segbits_gtp_common.rdb
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
--seg-fn-in build/segbits_gtp_common.rdb \
--seg-fn-out build/segbits_gtp_common.db
${XRAY_MASKMERGE} build/mask_gtp_common.db $(addsuffix /segdata_gtp_common.txt,$(SPECIMENS))
pushdb:
${XRAY_MERGEDB} gtp_common build/segbits_gtp_common.db
${XRAY_MERGEDB} mask_gtp_common build/mask_gtp_common.db
.PHONY: database pushdb

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{
"PLL0_CFG": {
"type": "BIN",
"values": [134150145],
"digits": 27
},
"PLL0_REFCLK_DIV": {
"type": "INT",
"values": [1, 2],
"encoding": [16, 0],
"digits": 5
},
"PLL0_FBDIV_45": {
"type": "INT",
"values": [4, 5],
"encoding": [0, 1],
"digits": 1
},
"PLL0_FBDIV": {
"type": "INT",
"values": [1, 2, 3, 4, 5],
"encoding": [16, 0, 1, 2, 3],
"digits": 6
},
"PLL0_LOCK_CFG": {
"type": "BIN",
"values": [511],
"digits": 9
},
"PLL0_INIT_CFG": {
"type": "BIN",
"values": [16711425],
"digits": 24
},
"RSVD_ATTR0": {
"type": "BIN",
"values": [65535],
"digits": 16
},
"PLL1_DMON_CFG": {
"type": "BIN",
"values": [1],
"digits": 1
},
"PLL0_DMON_CFG": {
"type": "BIN",
"values": [1],
"digits": 1
},
"COMMON_CFG": {
"type": "BIN",
"values": [4294836225],
"digits": 32
},
"PLL_CLKOUT_CFG": {
"type": "BIN",
"values": [255],
"digits": 8
},
"BIAS_CFG": {
"type": "BIN",
"values": [18445618199572250625],
"digits": 64
},
"RSVD_ATTR1": {
"type": "BIN",
"values": [65535],
"digits": 16
},
"PLL1_INIT_CFG": {
"type": "BIN",
"values": [16711425],
"digits": 24
},
"PLL1_LOCK_CFG": {
"type": "BIN",
"values": [511],
"digits": 9
},
"PLL1_REFCLK_DIV": {
"type": "INT",
"values": [1, 2],
"encoding": [16, 0],
"digits": 5
},
"PLL1_FBDIV_45": {
"type": "INT",
"values": [4, 5],
"encoding": [0, 1],
"digits": 1
},
"PLL1_FBDIV": {
"type": "INT",
"values": [1, 2, 3, 4, 5],
"encoding": [16, 0, 1, 2, 3],
"digits": 6
},
"PLL1_CFG": {
"type": "BIN",
"values": [134150145],
"digits": 27
}
}

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
from enum import Enum
from prjxray.segmaker import Segmaker
INT = "INT"
BIN = "BIN"
def bitfilter(frame, bit):
# Filter out interconnect bits.
if frame not in [28, 29]:
return False
return True
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
else:
assert param_type == BIN
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
segmk.compile(bitfilter=bitfilter)
segmk.write()
if __name__ == '__main__':
main()

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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
import random
from collections import namedtuple
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
from prjxray.db import Database
INT = "INT"
BIN = "BIN"
def gen_sites():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
if gridinfo.tile_type not in [
"GTP_COMMON",
"GTP_COMMON_MID_RIGHT",
"GTP_COMMON_MID_RIGHT",
]:
continue
for site_name, site_type in gridinfo.sites.items():
if site_type != "GTPE2_COMMON":
continue
return site_name, site_type
def main():
print('''
module top();
''')
site_name, site_type = gen_sites()
params = dict()
params['site'] = site_name
verilog_attr = ""
verilog_attr = "#("
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
attrs = json.load(attrs_file)
for param, param_info in attrs.items():
param_type = param_info["type"]
param_values = param_info["values"]
param_digits = param_info["digits"]
if param_type == INT:
value = random.choice(param_values)
value_str = value
else:
assert param_type == BIN
value = random.randint(0, param_values[0])
value_str = "{digits}'b{value:0{digits}b}".format(
value=value, digits=param_digits)
params[param] = value
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
print("(* KEEP, DONT_TOUCH *)")
print("GTPE2_COMMON {} gtp_common ();".format(verilog_attr))
print("endmodule")
with open('params.json', 'w') as f:
json.dump(params, f, indent=2)
if __name__ == '__main__':
main()