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clbram fuzzer misc temp tests 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-12-15 11:27:01 -08:00 committed by Tim 'mithro' Ansell
parent 259300a7d4
commit cbbdccf9e2
2 changed files with 6 additions and 3 deletions
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7
fuzzers/018-clbram/generate.py
View File

@ -51,7 +51,8 @@ for l in f:
WA7USED, WA8USED
'''
which = 'D'
if 0:
if 1:
print(loc, 1)
segmk.addtag(loc, "WA7USED", 1)
segmk.addtag(loc, "WA8USED", module == 'my_RAM256X1S')
else:
@ -75,8 +76,10 @@ for l in f:
# Only valid in D
if which == 'D':
segmk.addtag(loc, "%sLUT.RAM" % which, bel in ('RAM32X1S', 'RAM64X1S'))
if 0:
if 1:
segmk.addtag(loc, "WA7USED", 0)
#segmk.addtag(loc, "WA7USED", 1)
print(loc, 0)
segmk.addtag(loc, "WA8USED", 0)
segmk.addtag(loc, "WEMUX.CE", bels != ['LUT6', 'LUT6', 'LUT6', 'LUT6'])

2
fuzzers/018-clbram/top.py
View File

@ -135,7 +135,7 @@ for clbi in range(CLBN):
params += ', .N_%s(1)' % bel
else:
bel = random.choice(multi_bels_by)
if multis == 0:
if multis % 4 == 0:
# Force an all LUT6 SLICE
bel = 'LUT6'
params += ', .%c_%s(1)' % (belc, bel)