mirror of https://github.com/openXC7/prjxray.git
bram: old local files
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
fad97c9cb6
commit
c6bbfd8fe4
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@ -0,0 +1,2 @@
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/specimen_[0-9][0-9][0-9]/
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/seg_clbl[lm].segbits
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@ -0,0 +1,20 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_bramx.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} bram_l seg_bramx.segbits
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${XRAY_MERGEDB} bram_r seg_bramx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_*.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -0,0 +1,15 @@
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FIXME: ROI is SLICE_X12Y100:SLICE_X27Y149
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But we need something with BRAM
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export XRAY_ROI=SLICE_X6Y100:SLICE_X27Y149
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# Needed?
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# export XRAY_ROI_FRAMES="0x00020500:0x000208ff"
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source $XRAY_DIR/utils/environment.sh
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Solves SLICEM specific bits:
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-Shift register LUT (SRL)
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-Memory size
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-RAM vs LUT
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-Related muxes
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@ -0,0 +1,4 @@
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#!/bin/bash
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export XRAY_ROI=SLICE_X6Y100:SLICE_X27Y149
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export XRAY_ROI_FRAMES=0x00820000:0x00820080
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@ -0,0 +1,32 @@
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#!/usr/bin/env python3
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import sys, re, os
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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c2i = {'0': 0, '1': 1}
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segmk = segmaker("design.bits")
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print("Loading tags")
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'''
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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l = l.strip()
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module, loc, pdata, data = l.split(',')
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print(loc)
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segmk.addtag(loc, "STUFF", 1)
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for i, d in enumerate(pdata):
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# Keep dec convention used on LUT?
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segmk.addtag(loc, "BRAM.INITP[%04d]" % i, c2i[d])
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for i, d in enumerate(data):
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# Keep dec convention used on LUT?
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segmk.addtag(loc, "BRAM.INIT[%04d]" % i, c2i[d])
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segmk.compile()
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segmk.write()
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@ -0,0 +1,18 @@
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#!/bin/bash
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set -ex
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source ${XRAY_GENHEADER}
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,273 @@
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'''
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Need coverage for the following:
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RAM32X1S_N
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RAM32X1D
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RAM32M
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RAM64X1S_N
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RAM64X1D_N
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RAM64M
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RAM128X1S_N
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RAM128X1D
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RAM256X1S
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SRL16E_N
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SRLC32E_N
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Note: LUT6 was added to try to simplify reduction, although it might not be needed
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'''
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import random
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random.seed(0)
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import os
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import re
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def slice_xy():
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'''Return (X1, X2), (Y1, Y2) from XRAY_ROI, exclusive end (for range)'''
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# SLICE_X12Y100:SLICE_X27Y149
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# Note XRAY_ROI_GRID_* is something else
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m = re.match(r'SLICE_X(.*)Y(.*):SLICE_X(.*)Y(.*)', os.getenv('XRAY_ROI'))
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ms = [int(m.group(i + 1)) for i in range(4)]
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return ((ms[0], ms[2] + 1), (ms[1], ms[3] + 1))
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# 18 + 36 count in ROI
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DUTN = 10
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SLICEX, SLICEY = slice_xy()
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested DUTs: %s' % str(DUTN))
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def gen_bram18():
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# TODO: generate this from DB
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assert ((6, 28) == SLICEX)
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x = 0
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for y in range(40, 60):
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# caller may reject position if needs more room
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yield "RAMB18_X%dY%d" % (x, y)
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def gen_bram36():
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# TODO: generate this from DB
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assert ((6, 28) == SLICEX)
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x = 0
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for y in range(20, 29):
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# caller may reject position if needs more room
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yield "RAMB36_X%dY%d" % (x, y)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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print(
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'''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,pdata,data\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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loci = 0
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def make(module, gen_locs, pdatan, datan):
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global loci
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for loc in gen_locs():
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pdata = randbits(pdatan * 0x100)
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data = randbits(datan * 0x100)
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print(' %s #(' % module)
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for i in range(pdatan):
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print(
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" .INITP_%02X(256'b%s)," %
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(i, pdata[i * 256:(i + 1) * 256]))
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for i in range(datan):
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print(
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" .INIT_%02X(256'b%s)," % (i, data[i * 256:(i + 1) * 256]))
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print('.LOC("%s"))' % (loc, ))
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print(
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' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (loci, 8 * loci, 8 * loci))
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f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
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loci += 1
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#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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# RAMB18E1
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print(
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'''
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module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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for i in range(8):
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print(
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" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print()
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for i in range(0x40):
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print(
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" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print()
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print('''\
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(* LOC=LOC *)
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RAMB18E1 #(''')
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for i in range(8):
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print(' .INITP_%02X(INITP_%02X),' % (i, i))
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print()
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for i in range(0x40):
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print(' .INIT_%02X(INIT_%02X),' % (i, i))
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print()
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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print(
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'''
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module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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for i in range(16):
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print(
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" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print()
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for i in range(0x80):
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print(
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" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print()
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print('''\
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(* LOC=LOC *)
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RAMB36E1 #(''')
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for i in range(16):
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print(' .INITP_%02X(INITP_%02X),' % (i, i))
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print()
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for i in range(0x80):
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print(' .INIT_%02X(INIT_%02X),' % (i, i))
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print()
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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