Add Makefile to fuzzers/example/

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

fuzzers/example/.gitignore

@@ -1,15 +1,2 @@
-/.Xil/
-/design/
-/design.log
-/design.tcl
-/design.xdc
-/design.bit
-/design.bits
-/design.dcp
-/hd_visual/
-/vivado[_.]*
-/usage_statistics_webtalk.*
-/lutdata.txt
-/carrydata.txt
-/segdata.txt
+/specimen_[0-9][0-9][0-9]/
 /database.txt

fuzzers/example/Makefile

@@ -0,0 +1,18 @@
+
+N := 10
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database.txt: $(SPECIMENS_OK)
+	cat $(addsuffix /segdata.txt,$(SPECIMENS)) | ../../tools/segmatch > database.new
+	mv database.new database.txt
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf $(SPECIMENS)
+
+.PHONY: clean
+

fuzzers/example/design.v

@@ -1,9 +1,11 @@
-module top(input clk, din, stb, output dout);
-	reg [39:0] din_bits;
-	wire [76:0] dout_bits;
+`include "setseed.vh"
 
-	reg [39:0] din_shr;
-	reg [76:0] dout_shr;
+module top(input clk, din, stb, output dout);
+	reg [41:0] din_bits;
+	wire [78:0] dout_bits;
+
+	reg [41:0] din_shr;
+	reg [78:0] dout_shr;
 
 	always @(posedge clk) begin
 		if (stb) begin
@@ -11,11 +13,11 @@ module top(input clk, din, stb, output dout);
 			dout_shr <= dout_bits;
 		end else begin
 			din_shr <= {din_shr, din};
-			dout_shr <= {dout_shr, din_shr[39]};
+			dout_shr <= {dout_shr, din_shr[41]};
 		end
 	end
 
-	assign dout = dout_shr[76];
+	assign dout = dout_shr[78];
 
 	stuff stuff (
 		.clk(clk),
@@ -24,7 +26,7 @@ module top(input clk, din, stb, output dout);
 	);
 endmodule
 
-module stuff(input clk, input [39:0] din_bits, output [76:0] dout_bits);
+module stuff(input clk, input [41:0] din_bits, output [78:0] dout_bits);
 	picorv32 picorv32 (
 		.clk(clk),
 		.resetn(din_bits[0]),
@@ -38,13 +40,13 @@ module stuff(input clk, input [39:0] din_bits, output [76:0] dout_bits);
 	);
 
 	randluts randluts (
-		.din(din_bits[39:34]),
-		.dout(dout_bits[76:71])
+		.din(din_bits[41:34]),
+		.dout(dout_bits[78:71])
 	);
 endmodule
 
-module randluts(input [5:0] din, output [5:0] dout);
-	localparam integer N = 300;
+module randluts(input [7:0] din, output [7:0] dout);
+	localparam integer N = 250;
 
 	function [31:0] xorshift32(input [31:0] xorin);
 		begin
@@ -57,30 +59,31 @@ module randluts(input [5:0] din, output [5:0] dout);
 
 	function [63:0] lutinit(input [7:0] a, b);
 		begin
-			lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b}))));
-			lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a}))));
+			lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
+			lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
 		end
 	endfunction
 
-	wire [(N+1)*6-1:0] nets;
+	wire [(N+1)*8-1:0] nets;
 
-	assign nets[5:0] = din;
-	assign dout = nets[(N+1)*6-1:N*6];
+	assign nets[7:0] = din;
+	assign dout = nets[(N+1)*8-1:N*8];
 
 	genvar i, j;
 	generate
 		for (i = 0; i < N; i = i+1) begin:is
-			for (j = 0; j < 6; j = j+1) begin:js
+			for (j = 0; j < 8; j = j+1) begin:js
+				localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
 				LUT6 #(
 					.INIT(lutinit(i, j))
 				) lut (
-					.I0(nets[6*i+0]),
-					.I1(nets[6*i+1]),
-					.I2(nets[6*i+2]),
-					.I3(nets[6*i+3]),
-					.I4(nets[6*i+4]),
-					.I5(nets[6*i+5]),
-					.O(nets[6*i+6+j])
+					.I0(nets[8*i+(k+0)%8]),
+					.I1(nets[8*i+(k+1)%8]),
+					.I2(nets[8*i+(k+2)%8]),
+					.I3(nets[8*i+(k+3)%8]),
+					.I4(nets[8*i+(k+4)%8]),
+					.I5(nets[8*i+(k+5)%8]),
+					.O(nets[8*i+8+j])
 				);
 			end
 		end

fuzzers/example/generate.sh

@@ -1,9 +1,13 @@
 #!/bin/bash
 
 set -ex
-
 source ../../settings.sh
 
+test $# = 1
+test ! -e $1
+mkdir $1
+cd $1
+
 cat > design.xdc << EOT
 set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports clk]
 set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports din]
@@ -27,13 +31,15 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 EOT
 
+echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
+
 cat > design.tcl << EOT
-source "utilities.tcl"
+source "../utilities.tcl"
 create_project -force -part $XRAY_PART design design
 
 read_xdc design.xdc
-read_verilog design.v
-read_verilog picorv32.v
+read_verilog ../design.v
+read_verilog ../picorv32.v
 
 synth_design -top top
 place_design
@@ -69,9 +75,9 @@ EOT
 rm -rf design design.log
 vivado -nojournal -log design.log -mode batch -source design.tcl
 
-#../../tools/bitread -o design_roi.bits -zy < design_roi_partial.bit
-../../tools/bitread -F $XRAY_ROI_FRAMES -o design.bits -zy < design.bit
+#../../../tools/bitread -o design_roi.bits -zy < design_roi_partial.bit
+../../../tools/bitread -F $XRAY_ROI_FRAMES -o design.bits -zy < design.bit
 
-python3 segdata.py
-../../tools/segmatch < segdata.txt > database.txt
+python3 ../segdata.py
+#../../../tools/segmatch < segdata.txt > database.txt
 

fuzzers/example/segdata.py

@@ -11,7 +11,7 @@ luts = dict()
 carry = dict()
 
 print("Loading grid.")
-with open("../../gridinfo/grid-%s-db.json" % os.getenv("XRAY_PART"), "r") as f:
+with open("../../../gridinfo/grid-%s-db.json" % os.getenv("XRAY_PART"), "r") as f:
     grid = json.load(f)
 
 print("Loading bits.")

tools/segmatch.cc

@@ -36,7 +36,8 @@ void read_input()
 		if (token == "seg")
 		{
 			std::cin >> token;
-			assert(segdata.count(token) == 0);
+			while (segdata.count(token))
+				token += "_";
 			segptr = &segdata[token];
 			continue;
 		}