Merge pull request #518 from antmicro/remove-fuzz-054

fuzzers: remove fuzzer 054

fuzzers/054-pip-gfan/Makefile

@@ -1,3 +0,0 @@
-MAKETODO_FLAGS=--re "^INT_[LR].GFAN" --not-endswith ".GND_WIRE"
-include ../int_loop.mk
-

fuzzers/054-pip-gfan/README.md

@@ -1,6 +0,0 @@
-
-Fuzzer for INT PIPs driving the GFAN wires
-------------------------------------------
-
-Run this fuzzer a few times until it produces an empty todo.txt file (`make run` will run this loop).
-

fuzzers/054-pip-gfan/generate.py

@@ -1,57 +0,0 @@
-#!/usr/bin/env python3
-
-import re
-
-from prjxray.segmaker import Segmaker
-
-segmk = Segmaker("design.bits")
-
-tiledata = dict()
-pipdata = dict()
-ignpip = set()
-
-print("Loading tags from design.txt.")
-with open("design.txt", "r") as f:
-    for line in f:
-        tile, pip, src, dst, pnum, pdir = line.split()
-        _, pip = pip.split(".")
-        _, src = src.split("/")
-        _, dst = dst.split("/")
-        pnum = int(pnum)
-        pdir = int(pdir)
-
-        if tile not in tiledata:
-            tiledata[tile] = {"pips": set(), "srcs": set(), "dsts": set()}
-
-        if pip in pipdata:
-            assert pipdata[pip] == (src, dst)
-        else:
-            pipdata[pip] = (src, dst)
-
-        tiledata[tile]["pips"].add(pip)
-        tiledata[tile]["srcs"].add(src)
-        tiledata[tile]["dsts"].add(dst)
-
-        if pdir == 0:
-            tiledata[tile]["srcs"].add(dst)
-            tiledata[tile]["dsts"].add(src)
-
-        if pnum == 1 or pdir == 0 or not re.match(r"^GFAN", dst):
-            ignpip.add(pip)
-
-for tile, pips_srcs_dsts in tiledata.items():
-    pips = pips_srcs_dsts["pips"]
-    srcs = pips_srcs_dsts["srcs"]
-    dsts = pips_srcs_dsts["dsts"]
-
-    for pip, src_dst in pipdata.items():
-        src, dst = src_dst
-        if pip in ignpip:
-            pass
-        elif pip in pips:
-            segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
-        elif src_dst[1] not in dsts:
-            segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
-
-segmk.compile()
-segmk.write()

fuzzers/054-pip-gfan/generate.sh

@@ -1,11 +0,0 @@
-#!/bin/bash
-
-echo "test: $PWD"
-FUZDIR=$PWD
-source ${XRAY_GENHEADER}
-
-${XRAY_VIVADO} -mode batch -source ../generate.tcl
-
-${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
-python3 ../generate.py
-

fuzzers/054-pip-gfan/generate.tcl

@@ -1,96 +0,0 @@
-source "$::env(XRAY_DIR)/utils/utils.tcl"
-
-proc base_project {} {
-    create_project -force -part $::env(XRAY_PART) design design
-
-    read_verilog $::env(FUZDIR)/top.v
-    synth_design -top top
-
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
-    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
-
-    create_pblock roi
-    resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
-
-    set_property CFGBVS VCCO [current_design]
-    set_property CONFIG_VOLTAGE 3.3 [current_design]
-    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-    set_param tcl.collectionResultDisplayLimit 0
-
-    place_design
-    route_design
-}
-
-proc write_txtdata {filename} {
-    puts "Writing $filename."
-    set fp [open $filename w]
-    set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
-    if {$all_pips != {}} {
-        puts "Dumping pips."
-        foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
-            foreach pip [filter $all_pips "TILE == $tile"] {
-                set src_wire [get_wires -uphill -of_objects $pip]
-                set dst_wire [get_wires -downhill -of_objects $pip]
-                set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
-                set dir_prop [get_property IS_DIRECTIONAL $pip]
-                puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
-            }
-        }
-    }
-    close $fp
-}
-
-proc loop { line idx int_l_tile int_r_tile } {
-    set tile_type [lindex $line 0]
-    set dst_wire [lindex $line 1]
-    set src_wire [lindex $line 2]
-
-    if {$tile_type == "INT_L"} {set tile $int_l_tile; set other_tile $int_r_tile}
-    if {$tile_type == "INT_R"} {set tile $int_r_tile; set other_tile $int_l_tile}
-
-    set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
-            -of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
-
-    set mylut [create_cell -reference LUT1 mylut_$idx]
-    set_property -dict "LOC $driver_site BEL A6LUT" $mylut
-
-    set mynet [create_net mynet_$idx]
-    connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
-    route_via $mynet "$tile/$src_wire $tile/$dst_wire"
-}
-
-proc load_todo_lines {} {
-    set fp [open "../../todo.txt" r]
-    set todo_lines {}
-    for {gets $fp line} {$line != ""} {gets $fp line} {
-        lappend todo_lines [split $line .]
-    }
-    close $fp
-    return $todo_lines
-}
-
-proc run {} {
-    base_project
-
-    # write_checkpoint -force design.dcp
-
-    set todo_lines [load_todo_lines]
-    set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
-    set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
-
-    for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
-        set line [lindex $todo_lines $idx]
-        puts "== $idx: $line"
-        set int_l_tile [lindex $int_l_tiles $idx]
-        set int_r_tile [lindex $int_r_tiles $idx]
-        loop $line $idx $int_l_tile $int_r_tile
-    }
-
-    route_design
-    write_checkpoint -force design.dcp
-    write_bitstream -force design.bit
-    write_txtdata design.txt
-
-}
-
-run

fuzzers/054-pip-gfan/top.v

@@ -1,3 +0,0 @@
-module top (input i, output o);
-	assign o = i;
-endmodule

fuzzers/Makefile

@@ -40,9 +40,8 @@ $(eval $(call fuzzer,050-pip-seed,005-tilegrid))
 $(eval $(call fuzzer,051-pip-imuxlout,050-pip-seed))
 $(eval $(call fuzzer,052-pip-clkin,050-pip-seed))
 $(eval $(call fuzzer,053-pip-ctrlin,050-pip-seed))
-$(eval $(call fuzzer,054-pip-gfan,050-pip-seed))
 $(eval $(call fuzzer,055-pip-gnd,050-pip-seed))
-$(eval $(call fuzzer,056-pip-rem,051-pip-imuxlout 052-pip-clkin 053-pip-ctrlin 054-pip-gfan 055-pip-gnd))
+$(eval $(call fuzzer,056-pip-rem,051-pip-imuxlout 052-pip-clkin 053-pip-ctrlin 055-pip-gnd))
 $(eval $(call fuzzer,057-pip-bi,056-pip-rem))
 ifneq ($(QUICK),Y)
 $(eval $(call fuzzer,058-pip-hclk,056-pip-rem))