Add XADC INT and ICAP INT fuzzers to solve 2 of 4 missing INT columns.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/005-tilegrid/Makefile

@@ -11,6 +11,8 @@ TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += fifo_int/build/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += cfg_int/build/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
 GENERATE_FULL_ARGS=
 
 ifeq (${XRAY_DATABASE}, zynq7)
@@ -66,6 +68,9 @@ ps7_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 monitor/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd monitor && $(MAKE)
 
+monitor_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd monitor_int && $(MAKE)
+
 bram/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd bram && $(MAKE)
 
@@ -84,6 +89,9 @@ dsp_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 fifo_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd fifo_int && $(MAKE)
 
+cfg_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd cfg_int && $(MAKE)
+
 build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py \
 		--fn-in build/basicdb/tilegrid.json \
@@ -114,6 +122,8 @@ clean:
 	cd dsp_int && $(MAKE) clean
 	cd fifo_int && $(MAKE) clean
 	cd monitor && $(MAKE) clean
+	cd monitor_int && $(MAKE) clean
+	cd cfg_int && $(MAKE) clean
 
 .PHONY: database pushdb clean run
 

fuzzers/005-tilegrid/add_tdb.py

@@ -90,6 +90,8 @@ def run(fn_in, fn_out, verbose=False):
         ("dsp_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("fifo_int/build/segbits_tilegrid.tdb", int_frames, int_words),
         ("ps7_int/build/segbits_tilegrid.tdb", int_frames, int_words),
+        ("cfg_int/build/segbits_tilegrid.tdb", int_frames, int_words),
+        ("monitor_int/build/segbits_tilegrid.tdb", int_frames, int_words),
     ]
 
     for (tdb_fn, frames, words) in tdb_fns:

fuzzers/005-tilegrid/cfg_int/Makefile

@@ -0,0 +1,3 @@
+N ?= 4
+GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 0"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/cfg_int/generate.tcl

@@ -0,0 +1,19 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/cfg_int/top.py

@@ -0,0 +1,118 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        if gridinfo.tile_type != 'CFG_CENTER_MID':
+            continue
+
+        sites = {}
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type not in sites:
+                sites[site_type] = []
+            sites[site_type].append(site_name)
+
+        for site_type in sites:
+            sites[site_type].sort()
+
+        int_grid_x = loc.grid_x + 3
+        int_tile_type = 'INT_L'
+
+        int_tile_locs = []
+        for dy in range(-9, 12):
+            # Skip the VBREAK tile.
+            if dy != 6:
+                int_tile_locs.append((int_grid_x, loc.grid_y + dy), )
+
+        int_tiles = []
+        for int_tile_loc in int_tile_locs:
+            int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
+            assert int_gridinfo.tile_type == int_tile_type, (
+                int_gridinfo.tile_type, int_tile_type)
+
+            int_tiles.append(grid.tilename_at_loc(int_tile_loc))
+
+        yield tile_name, sites, int_tiles
+
+
+def write_params(params):
+    pinstr = 'tile,val\n'
+    for tile, (val) in sorted(params.items()):
+        pinstr += '%s,%s\n' % (tile, val)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top();
+    ''')
+
+    sites = list(gen_sites())
+
+    # Only on CFG_CENTER_MID expected.
+    assert len(sites) == 1
+    tile_name, sites, int_tiles = sites[0]
+
+    assert len(sites['ICAP']) == 2, len(sites['ICAP'])
+
+    # int_tiles[6]:
+    # IMUX43 -> ICAP1_I31 = 0
+    # IMUX42 -> ICAP1_I30 = toggle 0/1
+    # int_tiles[7]:
+    # IMUX43 -> ICAP1_I15 = 0
+    # IMUX42 -> ICAP1_I14 = toggle 0/1
+    # int_tiles[8]:
+    # IMUX43 -> ICAP1_CSIB = 0
+    # IMUX42 -> ICAP1_RDWRB = toggle 0/1
+
+    ICAP1_I30 = random.randint(0, 1)
+    ICAP1_I14 = random.randint(0, 1)
+    ICAP1_RDWRB = random.randint(0, 1)
+
+    params = {}
+    params[int_tiles[6]] = ICAP1_I30
+    params[int_tiles[7]] = ICAP1_I14
+    params[int_tiles[8]] = ICAP1_RDWRB
+
+    print(
+        """
+    wire [31:0] icap_i_{site};
+    wire icap_rdwrd_{site};
+    wire icap_csib_{site};
+
+    assign icap_i_{site}[31] = 0;
+    assign icap_i_{site}[30] = {ICAP1_I30};
+
+    assign icap_i_{site}[15] = 0;
+    assign icap_i_{site}[14] = {ICAP1_I14};
+
+    assign icap_csib_{site} = 0;
+    assign icap_rdwrb_{site} = {ICAP1_RDWRB};
+
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    ICAPE2 icap_{site} (
+        .I(icap_i_{site}),
+        .RDWRB(icap_rdwrb_{site}),
+        .CSIB(icap_csib_{site})
+    );
+    """.format(
+            site=sites['ICAP'][1],
+            ICAP1_I30=ICAP1_I30,
+            ICAP1_I14=ICAP1_I14,
+            ICAP1_RDWRB=ICAP1_RDWRB))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/005-tilegrid/monitor_int/Makefile

@@ -0,0 +1,3 @@
+N ?= 4
+GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 0"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/monitor_int/generate.tcl

@@ -0,0 +1,19 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/monitor_int/top.py

@@ -0,0 +1,102 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        found_xadc = False
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['XADC']:
+                found_xadc = True
+                break
+
+        if not found_xadc:
+            continue
+
+        int_grid_x = loc.grid_x + 3
+        int_tile_type = 'INT_L'
+
+        int_tile_locs = []
+        for dy in range(-1, 1):
+            int_tile_locs.append((int_grid_x, loc.grid_y + dy), )
+
+        int_tiles = []
+        for int_tile_loc in int_tile_locs:
+            int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
+            assert int_gridinfo.tile_type == int_tile_type, (
+                int_gridinfo.tile_type, int_tile_type)
+
+            int_tiles.append(grid.tilename_at_loc(int_tile_loc))
+
+        yield tile_name, int_tiles
+
+
+def write_params(params):
+    pinstr = 'tile,val\n'
+    for tile, (val) in sorted(params.items()):
+        pinstr += '%s,%s\n' % (tile, val)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top();
+    ''')
+
+    sites = list(gen_sites())
+
+    # Only on CFG_CENTER_MID expected.
+    assert len(sites) == 1
+    tile_name, int_tiles = sites[0]
+
+    # int_tiles[0]:
+    # IMUX43 -> XADC_CONVST = 0
+    # IMUX42 -> XADC_DWE = toggle 0/1
+    # int_tiles[1]:
+    # IMUX43 -> XADC_DI15 = 0
+    # IMUX42 -> XADC_DI14 = toggle 0/1
+
+    DWE = random.randint(0, 1)
+    DI14 = random.randint(0, 1)
+
+    params = {}
+    params[int_tiles[0]] = DWE
+    params[int_tiles[1]] = DI14
+
+    print(
+        """
+    wire [15:0] di;
+    wire dwe;
+    wire convst;
+
+    assign convst = 0;
+    assign dwe = {DWE};
+
+    assign di[15] = 0;
+    assign di[14] = {DI14};
+
+    (* KEEP, DONT_TOUCH *)
+    XADC xadc (
+        .DI(di),
+        .DWE(dwe),
+        .CONVST(convst)
+    );
+    """.format(
+            DWE=DWE,
+            DI14=DI14,
+        ))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()