vtemplate script

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

utils/vtemplate

@@ -0,0 +1,83 @@
+#!/usr/bin/env python
+import re
+import sys
+
+# maybe https://github.com/fukatani/Pyverilog-1
+
+txt = open(sys.argv[1], 'r').read()
+
+modname = None
+params = []
+ios = []
+
+for l in txt.split('\n'):
+    l = l.strip()
+
+    # module RAMB18E1 (
+    m = re.match(r'module (.*) ', l)
+    if m:
+        modname = m.group(1)
+        continue
+
+    # input CLKARDCLK,
+    # input [13:0] ADDRARDADDR,
+    # output [1:0] DOPBDOP
+    m = re.match(r'(input|output)( \[([0-9]*):([0:9]*)\] | )([a-zA-Z0-9_]+)', l)
+    if m:
+        name = m.group(5)
+        aio = m.group(1)
+
+        wout = None
+        width = m.group(2).strip()
+        if width:
+            mw = re.match(r'\[([0-9]*):([0:9]*)\]', width)
+            wl = int(mw.group(1))
+            wr = int(mw.group(2))
+            wout = (wl, wr)
+
+        ios.append((name, aio, wout))
+        continue
+
+    # parameter SIM_DEVICE = "VIRTEX6";
+    m = re.match(r'parameter([ ])([a-zA-Z0-9_]+) = (.+);', l)
+    if m:
+        #aio = m.group(1)
+        name = m.group(2)
+        defval = m.group(3)
+
+        wout = None
+        params.append((name, wout, defval))
+
+
+modinst = modname
+
+print '''\
+module my_%s (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC = "";
+''' % modname
+
+print '    %s #(' % modname
+for pi, p in enumerate(params):
+    name, wout, defval = p
+    comma = ',' if pi != len(params) - 1 else ''
+
+    print '            .%s(%s)%s' % (name, defval, comma)
+
+print '        ) %s (' % modinst
+
+dii = 0
+doi = 0
+for ioi, io in enumerate(ios):
+    name, aio, wout = io
+    comma = ',' if ioi != len(ios) - 1 else ');'
+
+    if aio == 'input':
+        wire = 'din[%d]' % dii
+        dii = (dii + 1) % 8
+    else:
+        wire = 'dout[%d]' % doi
+        doi += 1
+    print '            .%s(%s)%s' % (name, wire, comma)
+
+print 'endmodule'
+