timfuz: site delay cleanup

Signed-off-by: John McMaster <johndmcmaster@gmail.com>

fuzzers/007-timing/projects/project.tcl

@@ -193,5 +193,3 @@ proc write_info4 {} {
     puts "  Has interconnect: $lines_some_int"
 }
 
-write_info4
-

fuzzers/007-timing/tile_annotate.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 import timfuz
-from timfuz import loadc_Ads_bs, Ads2bounds, PREFIX_W, PREFIX_P, PREFIX_SITEW, sitew_s2vals
+from timfuz import loadc_Ads_bs, Ads2bounds, PREFIX_W, PREFIX_P, PREFIX_SW_EI, PREFIX_SW_EO, PREFIX_SW_I, sw_ei_s2vals, sw_eo_s2vals, sw_i_s2vals
 
 import sys
 import os
@@ -50,32 +50,59 @@ def add_pip_wire(tilej, bounds, verbose=False):
 def add_sites(tilej, bounds):
     # XXX: no source of truth currently
     # is there a way we could get this?
+    # Naming discussion https://github.com/SymbiFlow/prjxray/pull/126
 
     sitej = tilej.setdefault('sites', {})
-    for variable, bound in bounds.items():
+
-        # group delays by site
+    def add_ei():
-        site_type, site_pin, bel_type, bel_pin = sitew_s2vals(variable)
+        for variable, bound in bounds[PREFIX_SW_EI].items():
-        asitej = sitej.setdefault(site_type, {})
+            site_type, src_site_pin, dst_bel_type, dst_bel_pin = sw_ei_s2vals(
-        # group together?
+                variable)
-        # wish there was a way to do tuple keys
+            # ex: SLICEL:AX->AFF.D
-        k = ('%s:%s:%s' % (site_pin, bel_type, bel_pin))
+            k = (
-        #print(site_type, k)
+                '%s:%s->%s.%s' %
-        asitej[k] = bound
+                (site_type, src_site_pin, dst_bel_type, dst_bel_pin))
-    #nsites = sum([len(v) for v in sitej.values()])
+            sitej.setdefault(site_type, {})[k] = bound
-    print('Sites: added %u sites, %u site wires' % (len(sitej), len(bounds)))
+
+    def add_eo():
+        for variable, bound in bounds[PREFIX_SW_EO].items():
+            site_type, src_bel_type, src_bel_pin, dst_site_pin = sw_eo_s2vals(
+                variable)
+            # ex: SLICEL:AFF.Q->AQ
+            k = (
+                '%s:%s.%s->%s' %
+                (site_type, src_bel_type, src_bel_pin, dst_site_pin))
+            sitej.setdefault(site_type, {})[k] = bound
+
+    def add_i():
+        for variable, bound in bounds[PREFIX_SW_I].items():
+            site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin = sw_i_s2vals(
+                variable)
+            # ex: SLICEL:LUT6.O2->AFF.D
+            k = (
+                '%s:%s.%s->%s.%s' %
+                (site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin))
+            sitej.setdefault(site_type, {})[k] = bound
+
+    add_ei()
+    add_eo()
+    add_i()
+    print('Sites: added %u sites' % len(sitej))
+    print('Added site wires')
+    print('  Site external in: %u' % len(bounds[PREFIX_SW_EI]))
+    print('  Site external out: %u' % len(bounds[PREFIX_SW_EO]))
+    print('  Site internal: %u' % len(bounds[PREFIX_SW_I]))
 
 
 def sep_bounds(bounds):
     pw = {}
-    sites = {}
+    sites = {PREFIX_SW_EI: {}, PREFIX_SW_EO: {}, PREFIX_SW_I: {}}
     for k, v in bounds.items():
         prefix = k.split(':')[0]
-        if prefix == PREFIX_W:
+        if prefix in (PREFIX_W, PREFIX_P):
             pw[k] = v
-        elif prefix == PREFIX_P:
+        elif prefix in (PREFIX_SW_EI, PREFIX_SW_EO, PREFIX_SW_I):
-            pw[k] = v
+            sites[prefix][k] = v
-        elif prefix == PREFIX_SITEW:
-            sites[k] = v
         else:
             assert 0, 'Unknown delay: %s %s' % (k, prefix)
     return pw, sites

fuzzers/007-timing/timfuz.py

@@ -21,20 +21,46 @@ from benchmark import Benchmark
 # models do not overlap between PIPs and WIREs
 PREFIX_W = 'WIRE'
 PREFIX_P = 'PIP'
-# site wire (a to b)
+# extneral site wire (ie site a to b)
-PREFIX_SITEW = 'SITEW'
+PREFIX_SW_EI = 'SITEW-EI'
+PREFIX_SW_EO = 'SITEW-EO'
+# internal site wire (ie bel a to b within a site)
+PREFIX_SW_I = 'SITEW-I'
 
 
-def sitew_vals2s(site_type, site_pin, bel_type, bel_pin):
+def sw_ei_vals2s(site_type, src_site_pin, dst_bel, dst_bel_pin):
     '''Pack site wire components into a variable string'''
     return '%s:%s:%s:%s:%s' % (
-        PREFIX_SITEW, site_type, site_pin, bel_type, bel_pin)
+        PREFIX_SW_EI, site_type, src_site_pin, dst_bel, dst_bel_pin)
 
 
-def sitew_s2vals(s):
+def sw_ei_s2vals(s):
-    prefix, site_type, site_pin, bel_type, bel_pin = s.split(':')
+    prefix, site_type, src_site_pin, dst_bel, dst_bel_pin = s.split(':')
-    assert prefix == 'SITEW'
+    assert prefix == PREFIX_SW_EI
-    return site_type, site_pin, bel_type, bel_pin
+    return site_type, src_site_pin, dst_bel, dst_bel_pin
+
+
+def sw_eo_vals2s(site_type, src_bel, src_bel_pin, dst_site_pin):
+    return '%s:%s:%s:%s:%s' % (
+        PREFIX_SW_EO, site_type, src_bel, src_bel_pin, dst_site_pin)
+
+
+def sw_eo_s2vals(s):
+    prefix, site_type, src_bel, src_bel_pin, dst_site_pin = s.split(':')
+    assert prefix == PREFIX_SW_EO
+    return site_type, src_bel, src_bel_pin, dst_site_pin
+
+
+def sw_i_vals2s(site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin):
+    return '%s:%s:%s:%s:%s:%s' % (
+        PREFIX_SW_I, site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin)
+
+
+def sw_i_s2vals(s):
+    prefix, site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin = s.split(
+        ':')
+    assert prefix == PREFIX_SW_I
+    return site_type, src_bel, src_bel_pin, dst_bel, dst_bel_pin
 
 
 # Equations are filtered out until nothing is left

fuzzers/007-timing/timing_txt2scsv.py

@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-from timfuz import Benchmark, A_di2ds, PREFIX_SITEW, sitew_vals2s
+from timfuz import Benchmark, A_di2ds, sw_ei_vals2s, sw_eo_vals2s, sw_i_vals2s
 from timing_txt2json import gen_timing4a, load_speed_json
 
 import glob
@@ -59,8 +59,13 @@ def sd_parts(sd):
     site, bel_type, bel_pin = sd['bel_pin'].split('/')
     assert sd['site'] == site
     assert sd['bel'] == site + '/' + bel_type
-    site, site_pin = sd['site_pin'].split('/')
+
-    assert sd['site_pin'] == sd['site'] + '/' + site_pin
+    site_pin_str = sd['site_pin']
+    if site_pin_str:
+        site, site_pin = sd['site_pin'].split('/')
+        assert sd['site_pin'] == sd['site'] + '/' + site_pin
+    else:
+        site_pin = None
     return site_type, site_pin, bel_type, bel_pin
 
 
@@ -87,28 +92,47 @@ def run(speed_json_f, fout, fns_in, verbose=0, corner=None):
         bstr = ' '.join([str(x) for x in mkb(tsites)])
 
         # Identify inter site transaction (SITEI)
-        if val['src']['site_pin'] is None and val['dst']['site_pin'] is None:
+        if not val['src']['site_pin'] and not val['dst']['site_pin']:
             # add one delay model for the path
-            assert 0, 'FIXME: inter site transaction'
+            # XXX: can these be solved exactly?
-            row_ds = {'SITEI_BLAH': None}
+            # might still have fanout and such
-        else:
+
+            src_site_type, _src_site_pin, src_bel_type, src_bel_pin = sd_parts(
+                val['src'])
+            dst_site_type, _dst_site_pin, dst_bel_type, dst_bel_pin = sd_parts(
+                val['dst'])
+            assert src_site_type == dst_site_type
+            assert (src_bel_type, src_bel_pin) != (dst_bel_type, dst_bel_pin)
+
+            k = sw_i_vals2s(
+                src_site_type, src_bel_type, src_bel_pin, dst_bel_type,
+                dst_bel_pin)
+            row_ds = {k: 1}
+        elif val['src']['site_pin'] and val['dst']['site_pin']:
             # if it exits a site it should enter another (possibly the same site)
             # site in (SITEI) or site out (SITEO)?
             # nah, keep things simple and just call them SITEW
-            assert val['src']['site_pin'] and val['dst']['site_pin']
             row_ds = {}
 
-            def add_delay(sd):
+            def add_dst_delay():
-                site_type, site_pin, bel_type, bel_pin = sd_parts(sd)
+                sd = val['dst']
-                # there are _ in some of the names
+                site_type, src_site_pin, dst_bel, dst_bel_pin = sd_parts(sd)
-                # use some other chars
+                k = sw_ei_vals2s(site_type, src_site_pin, dst_bel, dst_bel_pin)
-                k = sitew_vals2s(site_type, site_pin, bel_type, bel_pin)
-                # even if its the same site src and dst, input and output should be different types
                 assert k not in row_ds
                 row_ds[k] = 1
 
-            add_delay(val['src'])
+            def add_src_delay():
-            add_delay(val['dst'])
+                sd = val['src']
+                site_type, dst_site_pin, src_bel, src_bel_pin = sd_parts(sd)
+                k = sw_eo_vals2s(site_type, src_bel, src_bel_pin, dst_site_pin)
+                assert k not in row_ds
+                row_ds[k] = 1
+
+            add_dst_delay()
+            add_src_delay()
+        else:
+            # dropped by the tcl script
+            raise Exception("FIXME: handle destination but no source")
 
         row_ico = 0
         items = [str(row_ico), bstr]