mirror of https://github.com/openXC7/prjxray.git
lutcfg wip
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
04d18c0add
commit
b854c5205c
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@ -4,6 +4,8 @@ SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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test -z $(fgrep CRITICAL vivado.log)
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segprint -z -D design.bits >design.txt
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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@ -1,6 +1,6 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 64;
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localparam integer DOUT_N = 8;
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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@ -26,13 +26,42 @@ module top(input clk, stb, di, output do);
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);
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endmodule
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module roi(input clk, input [63:0] din, output [7:0] dout);
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module roi(input clk, input [255:0] din, output [255:0] dout);
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clb_LUT6 clb_LUT6 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0]));
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clb_LUT6_2 clb_LUT6_2 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 1]));
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clb_LUT7A clb_LUT7A (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 2]));
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clb_LUT7B clb_LUT7B (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 3]));
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clb_LUT7AB clb_LUT7AB (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 4]));
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clb_LUT8 clb_LUT8 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 5]));
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clb_LUT6_2 clb_LUT6_2 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 1 +: 2]));
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clb_LUT7A clb_LUT7A (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 3]));
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clb_LUT7B clb_LUT7B (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 4]));
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clb_LUT7AB clb_LUT7AB (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 5 +: 2]));
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clb_LUT8 clb_LUT8 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 7]));
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/*
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BOUTMUX tests
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-CY: carry chain, skip for now
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-F8: already have above
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-O6: easy
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-O5: easy
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-XOR: carry, skip for now
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-B5Q: easy
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*/
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clb_BOUTMUX_CY clb_BOUTMUX_CY (.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 8]));
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clb_BOUTMUX_F8 clb_BOUTMUX_F8 (.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 9]));
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clb_BOUTMUX_O6 clb_BOUTMUX_O6 (.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 10]));
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clb_BOUTMUX_O5 clb_BOUTMUX_O5 (.clk(clk), .din(din[ 88 +: 8]), .dout(dout[ 11 +: 2]));
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clb_BOUTMUX_B5Q_IN_A clb_BOUTMUX_B5Q_IN_A (.clk(clk), .din(din[ 96 +: 8]), .dout(dout[ 13 +: 2]));
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clb_BOUTMUX_B5Q_IN_B clb_BOUTMUX_B5Q_IN_B (.clk(clk), .din(din[ 104 +: 8]), .dout(dout[ 15 +: 2]));
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clb_BOUTMUX_XOR clb_BOUTMUX_XOR (.clk(clk), .din(din[ 112 +: 8]), .dout(dout[ 17 ]));
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clb_CARRY4 clb_CARRY4 (.clk(clk), .din(din[ 120 +: 16]), .dout(dout[18 +: 8]));
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//CYINT
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clb_CYINT_0 clb_CYINT_0 (.clk(clk), .din(din[ 192 +: 8]), .dout(dout[192 +: 8]));
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clb_CYINT_1 clb_CYINT_1 (.clk(clk), .din(din[ 200 +: 8]), .dout(dout[200 +: 8]));
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clb_CYINT_AX clb_CYINT_AX (.clk(clk), .din(din[ 208 +: 8]), .dout(dout[208 +: 8]));
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clb_CYINT_CIN clb_CYINT_CIN (.clk(clk), .din(din[ 216 +: 8]), .dout(dout[216 +: 8]));
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clb_ACY0_O5 clb_ACY0_O5 (.clk(clk), .din(din[ 224 +: 8]), .dout(dout[224 +: 8]));
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clb_ACY0_AX clb_ACY0_AX (.clk(clk), .din(din[ 232 +: 8]), .dout(dout[232 +: 8]));
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clb_BCY0_O5 clb_BCY0_O5 (.clk(clk), .din(din[ 240 +: 8]), .dout(dout[240 +: 8]));
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clb_BCY0_AX clb_BCY0_AX (.clk(clk), .din(din[ 248 +: 8]), .dout(dout[248 +: 8]));
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endmodule
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module clb_LUT6 (input clk, input [7:0] din, output dout);
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@ -49,10 +78,10 @@ module clb_LUT6 (input clk, input [7:0] din, output dout);
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.O(dout));
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endmodule
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module clb_LUT6_2 (input clk, input [7:0] din, output dout);
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wire o5;
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wire o6;
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assign dout = o5 & o6;
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module clb_LUT6_2 (input clk, input [7:0] din, output [1:0] dout);
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wire o6, o5;
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assign dout[1] = o6;
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assign dout[0] = o5;
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(* LOC="SLICE_X16Y101", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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@ -130,10 +159,11 @@ module clb_LUT7B (input clk, input [7:0] din, output dout);
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.O(lutco));
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endmodule
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module clb_LUT7AB (input clk, input [7:0] din, output dout);
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module clb_LUT7AB (input clk, input [7:0] din, output [1:0] dout);
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wire lutdo, lutco, lutbo, lutao;
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wire lut7bo, lut7ao;
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assign dout = lut7bo & lut7ao;
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assign dout[1] = lut7bo;
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assign dout[0] = lut7ao;
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(* LOC="SLICE_X16Y104", BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
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@ -251,3 +281,389 @@ module clb_LUT8 (input clk, input [7:0] din, output dout);
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.O(lutao));
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endmodule
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//******************************************************************************
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//BOUTMUX tests
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module clb_BOUTMUX_CY (input clk, input [7:0] din, output dout);
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//Shady connections, just enough to keep it placed
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wire [3:0] cout;
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assign dout = cout[1];
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(* LOC="SLICE_X18Y100", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(cout), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI());
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endmodule
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//clb_BOUTMUX_F8: already have above as clb_LUT8
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module clb_BOUTMUX_F8 (input clk, input [7:0] din, output dout);
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wire lutdo, lutco, lutbo, lutao;
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wire lut7bo, lut7ao;
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wire lut8o;
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(* LOC="SLICE_X18Y101", BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(dout), .I0(lut7bo), .I1(lut7ao), .S(din[7]));
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(* LOC="SLICE_X18Y101", BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
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(* LOC="SLICE_X18Y101", BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
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(* LOC="SLICE_X18Y101", BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutdo));
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(* LOC="SLICE_X18Y101", BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutco));
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(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_CAFE_0000_0001)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutbo));
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(* LOC="SLICE_X18Y101", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(lutao));
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endmodule
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module clb_BOUTMUX_O6 (input clk, input [7:0] din, output dout);
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(* LOC="SLICE_X18Y102", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(dout));
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endmodule
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module clb_BOUTMUX_O5 (input clk, input [7:0] din, output [1:0] dout);
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wire o5, o6;
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assign dout[1] = o5;
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assign dout[0] = o6;
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(* LOC="SLICE_X18Y103", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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endmodule
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//B5FFMUX positions
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module clb_BOUTMUX_B5Q_IN_A (input clk, input [7:0] din, output [1:0] dout);
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wire o5;
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wire o6;
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assign dout[0] = o6;
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(* LOC="SLICE_X18Y104", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC="SLICE_X18Y104", BEL="B5FF" *)
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FDPE ff (
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.C(clk),
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.Q(dout[1]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(o5)
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);
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endmodule
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//FIXME: failed
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module clb_BOUTMUX_B5Q_IN_B (input clk, input [7:0] din, output [1:0] dout);
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(* LOC="SLICE_X18Y105", BEL="B5FF" *)
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FDPE ff (
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.C(clk),
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.Q(dout[1]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(din[2])
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);
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endmodule
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//clb_BOUTMUX_XOR: carry, skip for now
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module clb_BOUTMUX_XOR (input clk, input [7:0] din, output dout);
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//Shady connections, just enough to keep it placed
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wire [3:0] o;
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assign dout = o[1];
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(* LOC="SLICE_X18Y106", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI());
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endmodule
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module clb_CARRY4 (input clk, input [15:0] din, output [7:0] dout);
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//CARRY4 carry4(.O(dout[3:0]), .CO(dout[7:4]), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[8]), .CI(din[9]));
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//CI must come from an adjacent CARRY4
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//CO however is routable out
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//Note: its folding the FFs in
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//are they in bypass? is that a thing?
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//I bet they are setup as latches
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(* LOC="SLICE_X18Y107", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(dout[3:0]), .CO(dout[7:4]), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[8]), .CI());
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endmodule
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//****************************************************************
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//CYINT
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module clb_CYINT_0 (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] o;
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assign dout[0] = o[1];
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(* LOC="SLICE_X20Y100", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI());
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endmodule
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module clb_CYINT_1 (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] o;
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assign dout[0] = o[1];
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(* LOC="SLICE_X20Y101", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b1), .CI());
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endmodule
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module clb_CYINT_AX (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] o;
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assign dout[0] = o[1];
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(* LOC="SLICE_X20Y102", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI());
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endmodule
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module clb_CYINT_CIN (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] coutl;
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wire [3:0] outr;
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assign dout[0] = outr[1];
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//Hmm it actually goes by Y, not L/R as shown in wire layout
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(* LOC="SLICE_X20Y103", KEEP, DONT_TOUCH *)
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CARRY4 carry4l(.O(), .CO(coutl), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[8]), .CI());
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(* LOC="SLICE_X20Y104", KEEP, DONT_TOUCH *)
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CARRY4 carry4r(.O(outr), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[8]), .CI(coutl[3]));
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endmodule
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//******************************************************************************
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//ACY0
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module clb_ACY0_AX (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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(* LOC="SLICE_X20Y105", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC="SLICE_X20Y105", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S({din[7:5], o6}), .CYINIT(1'b0), .CI());
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endmodule
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module clb_ACY0_O5 (input clk, input [7:0] din, output [7:0] dout);
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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(* LOC="SLICE_X20Y106", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC="SLICE_X20Y106", KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI({din[3:1], o5}), .S({din[7:5], o6}), .CYINIT(1'b0), .CI());
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endmodule
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module clb_BCY0_AX (input clk, input [7:0] din, output [7:0] dout);
|
||||
wire [3:0] o;
|
||||
assign dout[0] = o[1];
|
||||
wire o6, o5;
|
||||
reg [3:0] s;
|
||||
|
||||
always @(*) begin
|
||||
s = din[7:4];
|
||||
s[1] = o6;
|
||||
end
|
||||
|
||||
(* LOC="SLICE_X20Y107", BEL="B6LUT", KEEP, DONT_TOUCH *)
|
||||
LUT6_2 #(
|
||||
.INIT(64'h8000_0000_0000_0001)
|
||||
) lut (
|
||||
.I0(din[0]),
|
||||
.I1(din[1]),
|
||||
.I2(din[2]),
|
||||
.I3(din[3]),
|
||||
.I4(din[4]),
|
||||
.I5(din[5]),
|
||||
.O5(o5),
|
||||
.O6(o6));
|
||||
|
||||
(* LOC="SLICE_X20Y107", KEEP, DONT_TOUCH *)
|
||||
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
|
||||
endmodule
|
||||
|
||||
module clb_BCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
|
||||
wire [3:0] o;
|
||||
assign dout[0] = o[1];
|
||||
wire o6, o5;
|
||||
reg [3:0] s;
|
||||
reg [3:0] di;
|
||||
|
||||
always @(*) begin
|
||||
s = din[7:4];
|
||||
s[1] = o6;
|
||||
|
||||
di = {din[3:0]};
|
||||
di[1] = o5;
|
||||
end
|
||||
|
||||
(* LOC="SLICE_X20Y108", BEL="B6LUT", KEEP, DONT_TOUCH *)
|
||||
LUT6_2 #(
|
||||
.INIT(64'h8000_0000_0000_0001)
|
||||
) lut (
|
||||
.I0(din[0]),
|
||||
.I1(din[1]),
|
||||
.I2(din[2]),
|
||||
.I3(din[3]),
|
||||
.I4(din[4]),
|
||||
.I5(din[5]),
|
||||
.O5(o5),
|
||||
.O6(o6));
|
||||
|
||||
(* LOC="SLICE_X20Y108", KEEP, DONT_TOUCH *)
|
||||
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
|
||||
endmodule
|
||||
|
||||
|
||||
module clb_NCY0_AX (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC="SLICE_X16Y129_FIXME";
|
||||
parameter BEL="A6LUT_FIXME";
|
||||
|
||||
wire [3:0] o;
|
||||
assign dout[0] = o[1];
|
||||
wire o6, o5;
|
||||
reg [3:0] s;
|
||||
|
||||
always @(*) begin
|
||||
s = din[7:4];
|
||||
s[1] = o6;
|
||||
end
|
||||
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
LUT6_2 #(
|
||||
.INIT(64'h8000_0000_0000_0001)
|
||||
) lut (
|
||||
.I0(din[0]),
|
||||
.I1(din[1]),
|
||||
.I2(din[2]),
|
||||
.I3(din[3]),
|
||||
.I4(din[4]),
|
||||
.I5(din[5]),
|
||||
.O5(o5),
|
||||
.O6(o6));
|
||||
|
||||
(* LOC=LOC, KEEP, DONT_TOUCH *)
|
||||
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
|
||||
endmodule
|
||||
|
||||
module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
|
||||
wire [3:0] o;
|
||||
assign dout[0] = o[1];
|
||||
wire o6, o5;
|
||||
reg [3:0] s;
|
||||
reg [3:0] di;
|
||||
|
||||
always @(*) begin
|
||||
s = din[7:4];
|
||||
s[1] = o6;
|
||||
|
||||
di = {din[3:0]};
|
||||
di[1] = o5;
|
||||
end
|
||||
|
||||
(* LOC="SLICE_X20Y108", BEL="B6LUT", KEEP, DONT_TOUCH *)
|
||||
LUT6_2 #(
|
||||
.INIT(64'h8000_0000_0000_0001)
|
||||
) lut (
|
||||
.I0(din[0]),
|
||||
.I1(din[1]),
|
||||
.I2(din[2]),
|
||||
.I3(din[3]),
|
||||
.I4(din[4]),
|
||||
.I5(din[5]),
|
||||
.O5(o5),
|
||||
.O6(o6));
|
||||
|
||||
(* LOC="SLICE_X20Y108", KEEP, DONT_TOUCH *)
|
||||
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue