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Ran format-py 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-10 16:15:28 +02:00
parent 1e6b85b8a8
commit b7fc6734d2
4 changed files with 12 additions and 5 deletions
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2
fuzzers/015-clb-nffmux/generate.py
View File

@ -67,6 +67,7 @@ for loc, muxes in cache.items():
tag = "%sFFMUX.%s" % (which, src)
segmk.add_site_tag(loc, tag, 0)
def bitfilter(frame_idx, bit_idx):
# Since the SRL32 is enabled along with DFFMUX.MC31, bits related to
@ -79,5 +80,6 @@ def bitfilter(frame_idx, bit_idx):
return util.bitfilter_clb_mux(frame_idx, bit_idx)
segmk.compile(bitfilter=bitfilter)
segmk.write()

3
fuzzers/015-clb-nffmux/top.py
View File

@ -9,16 +9,19 @@ INCREMENT = os.getenv('CLBN', 0)
CLBN = 600 + int(INCREMENT)
print('//Requested CLBs: %s' % str(CLBN))
def gen_slicels():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEL']):
yield site_name
def gen_slicems():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEM']):
yield site_name
DIN_N = CLBN * 8
DOUT_N = CLBN * 8

2
fuzzers/016-clb-noutmux/top.py
View File

@ -9,6 +9,7 @@ INCREMENT = os.getenv('CLBN', 0)
CLBN = 600 + int(INCREMENT)
print('//Requested CLBs: %s' % str(CLBN))
def gen_slicels():
for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
['SLICEL']):
@ -20,6 +21,7 @@ def gen_slicems():
['SLICEM']):
yield site_name
DIN_N = CLBN * 8
DOUT_N = CLBN * 8