docs: Import wiki pages.

* Interconnect page.
 * Reference page.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

docs/architecture/interconnect.rst

@@ -0,0 +1,26 @@
+Interconnect PIPs
+=================
+
+Fake PIPs
+---------
+
+Some PIPs are not "real", in the sense that no bit pattern in the bit-stream correspond to the PIP being used. This is the case for all the PIPs in the switchbox in a CLB tile (ex: CLBLM_L_INTER): They either correspond to buffers that are always on (i.e. 1:1 connections such as `CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0`), or they correspond to permutations of LUT input signals, which is handled by changing the LUT init value accordingly, or they are used to "connect" two signals that are driven by the same signal from within the CLB.
+
+The bit switchbox in an INT tile also contains a few 1:1 connections that are in fact always present and have no corresponding configuration bits.
+
+Regular PIPs
+------------
+
+Regular PIPs correspond to a bit pattern that is present in the bit stream when the PIP is used in the current design. There is a block of up to 10-ish bits for each destination signal. For each configuration (i.e. source net that can drive the destination) there is a pair of bits that is set.
+
+For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an INT_L tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring PIPs.
+
+VCC Drivers
+-----------
+
+The default state for a net is to be driven high. The PIPs that drive a net from `VCC_WIRE` correspond to the "empty configuration" with no bits set.
+
+Bidirectional PIPs
+------------------
+
+Bidirectional PIPs are used to stitch together long traces (LV*, LVB*). In case of bidirectional PIPs there are two different configuration patterns, one for each direction.

docs/architecture/reference.rst

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+References
+==========
+
+Xilinx documents one should be familiar with:
+---------------------------------------------
+
+### UG470: 7 Series FPGAs Configuration User Guide
+
+https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+
+*Chapter 5: Configuration Details* contains a good description of the overall
+bit-stream format. (See section "Bitstream Composition" and following.)
+
+### UG912: Vivado Design Suite Properties Reference Guide
+
+http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug912-vivado-properties.pdf
+
+Contains an excellent description of the in-memory data structures and
+associated properties Vivado uses to describe the design and the chip. The TCL
+interface provides a convenient interface to access this information.
+
+### UG903: Vivado Design Suite User Guide: Using Constraints
+
+http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug903-vivado-using-constraints.pdf
+
+The fuzzers generate designs (HDL + Constraints) that use many physical
+contraints constraints (placement and routing) to produce bit-streams with
+exactly the desired features. It helps to learn about the available constraints
+before starting to write fuzzers.
+
+### UG901: Vivado Design Suite User Guide: Synthesis
+
+http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug901-vivado-synthesis.pdf
+
+*Chapter 2: Synthesis Attributes* contains an overview of the Verilog
+attributes that can be used to control Vivado Synthesis. Many of them
+are useful for writing fuzzer designs. There is some natural overlap
+with UG903.
+
+### UG909: Vivado Design Suite User Guide: Partial Reconfiguration
+
+https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug909-vivado-partial-reconfiguration.pdf
+
+Among other things this UG contains some valuable information on how to constrain a design in a way so that the items inside a pblock are strictly separate from the items outside that pblock.
+
+### UG474: 7 Series FPGAs Configurable Logic Block
+
+https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
+
+Describes the capabilities of a CLB, the most important non-interconnect resource of a Xilinx FPGA.
+
+Other documentation that might be of use:
+-----------------------------------------
+
+Doc of .bit container file format:
+http://www.pldtool.com/pdf/fmt_xilinxbit.pdf
+
+Open-Source Bitstream Generation for FPGAs, Ritesh K Soni, Master Thesis:
+https://vtechworks.lib.vt.edu/bitstream/handle/10919/51836/Soni_RK_T_2013.pdf
+
+VTR-to-Bitstream, Eddie Hung:
+https://eddiehung.github.io/vtb.html
+
+From the bitstream to the netlist, Jean-Baptiste Note and Éric Rannaud:
+http://www.fabienm.eu/flf/wp-content/uploads/2014/11/Note2008.pdf
+
+Wolfgang Spraul's Spartan-6 (xc6slx9) project:
+https://github.com/Wolfgang-Spraul/fpgatools
+
+Marek Vasut's Typhoon Cyclone IV project:
+http://git.bfuser.eu/?p=marex/typhoon.git
+
+XDL generator/imported for Vivado:
+https://github.com/byuccl/tincr
+

docs/index.rst

@@ -20,8 +20,10 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    architecture/overview
    architecture/configuration
    architecture/bitstream_format
+   architecture/interconnect
    architecture/dram_configuration
    architecture/glossary
+   architecture/reference
 
 .. toctree::
    :maxdepth: 2