clbram: ignore LUTs with non-expected contents

Signed-off-by: John McMaster <johndmcmaster@gmail.com>

fuzzers/018-clbram/generate.py

@@ -2,6 +2,8 @@
 
 from prjxray.segmaker import Segmaker
 
+verbose = False
+
 segmk = Segmaker("design.bits")
 
 # Can fit 4 per CLB
@@ -16,6 +18,20 @@ multi_bels_bn = [
     'RAM64X1S',
 ]
 
+
+def load_tcl():
+    f = open('design.csv', 'r')
+    f.readline()
+    ret = {}
+    for l in f:
+        l = l.strip()
+        tile, site, bel, cell, ref_name, prim_type = l.split(',')
+        ret[bel] = ref_name
+    return ret
+
+
+design = load_tcl()
+
 print("Loading tags")
 '''
 module,loc,bela,belb,belc,beld
@@ -34,6 +50,8 @@ for l in f:
         module in ('my_RAM128X1D', 'my_RAM128X1S_N', 'my_RAM256X1S'))
     segmk.add_site_tag(loc, "WA8USED", module == 'my_RAM256X1S')
 
+    bels_tcl = [design.get("%s/%c6LUT" % (loc, bel), None) for bel in "ABCD"]
+
     # (a, b, c, d)
     # Size set for RAM32X1S, RAM32X1D, and SRL16E
     size = [0, 0, 0, 0]
@@ -42,9 +60,14 @@ for l in f:
     # RAM set for RAM* primitives
     ram = [0, 0, 0, 0]
 
+    verbose and print('%s' % loc)
+    verbose and print('  %s %s %s %s' % tuple(bels_tcl))
+
     if module == 'my_ram_N':
         # Each one of: SRL16E, SRLC32E, LUT6
         bels = [p0, p1, p2, p3]
+        verbose and print('  %s %s %s %s' % tuple(bels))
+        assert bels == bels_tcl
 
         # Clock Enable (CE) clock gate only enabled if we have clocked elements
         # A pure LUT6 does not, but everything else should
@@ -80,14 +103,15 @@ for l in f:
             (0, 0, 1, 1),
             (1, 1, 1, 1),
         ]
+        has_bel_tcl = tuple([int(bool(x)) for x in bels_tcl])
 
         # Always use all 4 sites
         if module in ('my_RAM32M', 'my_RAM64M', 'my_RAM128X1D',
                       'my_RAM256X1S'):
-            ram = [1, 1, 1, 1]
+            ram = (1, 1, 1, 1)
         # Only can occupy CD I guess
         elif module == 'my_RAM32X1D':
-            ram = [0, 0, 1, 1]
+            ram = (0, 0, 1, 1)
         # Uses 2 sites at a time
         elif module in ('my_RAM64X1D_N', 'my_RAM128X1S_N'):
             ram = pack2[n - 1]
@@ -96,6 +120,13 @@ for l in f:
             ram = pack4[n - 1]
         else:
             assert (0)
+        verbose and print('  %s %s %s %s' % tuple(ram))
+        verbose and print('  %s %s %s %s' % tuple(has_bel_tcl))
+        # assert ram == ram_tcl
+        # Hack: reject if something unexpected got packed in
+        # TODO: place dummy LUTs to exclude placement?
+        if ram != has_bel_tcl:
+            continue
 
         # All entries here require D
         assert (ram[3])
@@ -108,6 +139,8 @@ for l in f:
             size = [1, 1, 1, 1]
         elif module == 'my_RAM32X1S_N':
             size = pack4[n - 1]
+            if size != has_bel_tcl:
+                continue
         else:
             assert (not module.startswith('my_RAM32'))
 

fuzzers/018-clbram/generate.tcl

@@ -1,26 +1,66 @@
-create_project -force -part $::env(XRAY_PART) design design
+proc build {} {
-read_verilog top.v
+    create_project -force -part $::env(XRAY_PART) design design
-synth_design -top top
+    read_verilog top.v
+    synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
 
-create_pblock roi
+    create_pblock roi
 
-add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+    add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+    resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 
-set_property CFGBVS VCCO [current_design]
+    set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-set_param tcl.collectionResultDisplayLimit 0
+    set_param tcl.collectionResultDisplayLimit 0
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
-place_design
+    place_design
-route_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+proc dump {} {
+    set roi [get_pblocks roi]
+
+    set fp [open "design.csv" w]
+    puts $fp "tile,site,bel,cell,ref_name,prim_type"
+
+    set sites [get_sites -of_objects $roi]
+    for {set sitei 0} {$sitei < [llength $sites]} {incr sitei} {
+        # set site [get_sites SLICE_X6Y105]
+        set site [lindex $sites $sitei]
+        set tile [get_tiles -of_objects $site]
+
+        set bels [get_bels -of_objects $site -filter {TYPE == LUT_OR_MEM6}]
+        for {set beli 0} {$beli < [llength $bels]} {incr beli} {
+            # set bel [get_bels SLICE_X6Y105/D6LUT]
+            set bel [lindex $bels $beli]
+            set cell [get_cells -of_objects $bel]
+            if { "$cell" == "" } {
+                continue
+            }
+            # Ex SRL16E
+            set ref_name [get_property REF_NAME $cell]
+            # Ex: DMEM.srl.SRL16E
+            set prim_type [get_property PRIMITIVE_TYPE $cell]
+            puts $fp "$tile,$site,$bel,$cell,$ref_name,$prim_type"
+        }
+    }
+    close $fp
+}
+
+proc run {} {
+    build
+    dump
+}
+
+run
 
-write_checkpoint -force design.dcp
-write_bitstream -force design.bit