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Added solution for some additional MMCM features 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2020-11-03 15:30:35 +01:00
parent 6bf585ba72
commit af0b0a7657
2 changed files with 25 additions and 0 deletions
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5
fuzzers/031-cmt-mmcm/generate.py
View File

@ -35,6 +35,8 @@ def bus_tags(segmk, ps, site):
('RST', 1),
('PWRDWN', 1),
('CLKINSEL', 0),
('PSEN', 1),
('PSINCDEC', 1),
]:
opt = 'IS_{}_INVERTED'.format(reg)
@ -130,6 +132,9 @@ def bus_tags(segmk, ps, site):
# site, 'COMPENSATION.INTERNAL',
# verilog.unquote(ps['COMPENSATION']) in ['INTERNAL'])
opt = (verilog.unquote(ps["SS_EN"]) == "TRUE")
segmk.add_site_tag(site, "SS_EN", opt)
for param in ['CLKFBOUT_MULT_F']:
paramadj = int(ps[param])
bitstr = [int(x) for x in "{0:09b}".format(paramadj)[::-1]]

20
fuzzers/031-cmt-mmcm/top.py
View File

@ -31,6 +31,13 @@ def gen_sites():
yield tile_name, tile_type, site_name
def gen_true_false(p):
if random.random() <= p:
return verilog.quote("TRUE")
else:
return verilog.quote("FALSE")
def main():
sites = sorted(list(gen_sites()))
max_sites = len(sites)
@ -100,6 +107,10 @@ module top(
random.randint(0, 1),
"IS_CLKINSEL_INVERTED":
random.randint(0, 1),
"IS_PSEN_INVERTED":
random.randint(0, 1),
"IS_PSINCDEC_INVERTED":
random.randint(0, 1),
"CLKFBOUT_MULT_F":
random.randint(2, 4),
"CLKOUT0_DIVIDE_F":
@ -136,8 +147,14 @@ module top(
'HIGH',
'LOW',
))),
"SS_EN":
gen_true_false(0.15),
}
# SS_EN requires BANDWIDTH to be LOW
if verilog.unquote(params["SS_EN"]) == "TRUE":
params["BANDWIDTH"] = verilog.quote("LOW")
if verilog.unquote(params['COMPENSATION']) == 'ZHOLD':
params['clkfbin_conn'] = random.choice(
(
@ -239,6 +256,8 @@ module top(
.IS_RST_INVERTED({IS_RST_INVERTED}),
.IS_PWRDWN_INVERTED({IS_PWRDWN_INVERTED}),
.IS_CLKINSEL_INVERTED({IS_CLKINSEL_INVERTED}),
.IS_PSEN_INVERTED({IS_PSEN_INVERTED}),
.IS_PSINCDEC_INVERTED({IS_PSINCDEC_INVERTED}),
.CLKOUT0_DIVIDE_F({CLKOUT0_DIVIDE_F}),
.CLKOUT1_DIVIDE({CLKOUT1_DIVIDE}),
.CLKOUT2_DIVIDE({CLKOUT2_DIVIDE}),
@ -252,6 +271,7 @@ module top(
.CLKOUT0_DUTY_CYCLE({CLKOUT0_DUTY_CYCLE}),
.COMPENSATION({COMPENSATION}),
.BANDWIDTH({BANDWIDTH}),
.SS_EN({SS_EN}),
.CLKIN1_PERIOD(10.0),
.CLKIN2_PERIOD(10.0)
) pll_{site} (