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Merge pull request #1604 from antmicro/add-pcie-ppips 

071-ppips: add pcie-related ppips
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litghost 2021-03-08 12:53:47 -08:00 committed by GitHub
parent 0941a21ddb 15eae051f8
commit aef20ce6dc
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1 changed files with 76 additions and 0 deletions
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76
fuzzers/071-ppips/generate.tcl
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@ -214,6 +214,64 @@ proc write_gtp_int_interface_ppips_db {filename tile tile_suffix wire_suffix} {
close $fp
}
proc write_pcie_ppips_db {filename tile tile_suffix} {
set fp [open $filename "w"]
set tile [get_tiles $tile]
set tile_type [get_property TILE_TYPE $tile]
foreach pip [get_pips -of_objects $tile] {
set dst_wire [get_wires -downhill -of_objects $pip]
if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
set src_wire [get_wires -uphill -of_objects $pip]
if {![regexp "PCIE" $src_wire]} {
continue
}
puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
}
}
close $fp
}
proc write_pcie_int_interface_ppips_db {filename tile allows forbids} {
set fp [open $filename "w"]
set tile [get_tiles $tile]
set tile_type [get_property TILE_TYPE $tile]
foreach pip [get_pips -of_objects $tile] {
set dst_wire [get_wires -downhill -of_objects $pip]
set src_wire [get_wires -uphill -of_objects $pip]
set skip_wire false
foreach wire $forbids {
if {[regexp $wire $dst_wire]} {
set skip_wire true
break
}
}
if {$skip_wire == true} {
continue
}
set skip_wire true
foreach wire $allows {
if {[regexp $wire $dst_wire]} {
set skip_wire false
break
}
}
if {$skip_wire == true} {
continue
}
puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
}
close $fp
}
foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {
@ -290,3 +348,21 @@ foreach tile_type {GTP_INT_INTERFACE} {
write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type]_l.db" $tile "_L" "_LEFT"
}
}
foreach tile_type {PCIE_BOT PCIE_TOP} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {
set tile [lindex $tiles 0]
write_pcie_ppips_db "ppips_[string tolower $tile_type].db" $tile ""
}
}
foreach tile_type {PCIE_INT_INTERFACE_L PCIE_INT_INTERFACE_R} {
set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
if {[llength $tiles] != 0} {
set tile [lindex $tiles 0]
set allow_wires {"IMUX_OUT" "IMUX_L" "LOGIC_OUTS"}
set forbid_wires {"DELAY"}
write_pcie_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile $allow_wires $forbid_wires
}
}