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clb_n5ffmux minitest 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-12-01 13:46:09 -08:00 committed by Tim 'mithro' Ansell
parent fcae0c0117
commit aea7788f6a
18 changed files with 362 additions and 138 deletions
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0
minitests/ncy0/.gitignore → minitests/clb_cfg/.gitignore vendored
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0
minitests/lutcfg/Makefile → minitests/clb_cfg/Makefile
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0
minitests/lutcfg/README.txt → minitests/clb_cfg/README.txt
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0
minitests/lutcfg/runme.sh → minitests/clb_cfg/runme.sh
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0
minitests/lutcfg/runme.tcl → minitests/clb_cfg/runme.tcl
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230
minitests/lutcfg/top.v → minitests/clb_cfg/top.v
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@ -1,3 +1,5 @@
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
@ -58,10 +60,14 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
clb_CYINT_AX clb_CYINT_AX (.clk(clk), .din(din[ 208 +: 8]), .dout(dout[208 +: 8]));
clb_CYINT_CIN clb_CYINT_CIN (.clk(clk), .din(din[ 216 +: 8]), .dout(dout[216 +: 8]));
clb_ACY0_O5 clb_ACY0_O5 (.clk(clk), .din(din[ 224 +: 8]), .dout(dout[224 +: 8]));
clb_ACY0_AX clb_ACY0_AX (.clk(clk), .din(din[ 232 +: 8]), .dout(dout[232 +: 8]));
clb_BCY0_O5 clb_BCY0_O5 (.clk(clk), .din(din[ 240 +: 8]), .dout(dout[240 +: 8]));
clb_BCY0_AX clb_BCY0_AX (.clk(clk), .din(din[ 248 +: 8]), .dout(dout[248 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y100"), .N(0))
clb_N5FFMUX_0 (.clk(clk), .din(din[ 224 +: 8]), .dout(dout[224 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y101"), .N(1))
clb_N5FFMUX_1 (.clk(clk), .din(din[ 232 +: 8]), .dout(dout[232 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y102"), .N(2))
clb_N5FFMUX_2 (.clk(clk), .din(din[ 240 +: 8]), .dout(dout[240 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y103"), .N(3))
clb_N5FFMUX_3 (.clk(clk), .din(din[ 248 +: 8]), .dout(dout[248 +: 8]));
endmodule
module clb_LUT6 (input clk, input [7:0] din, output dout);
@ -496,174 +502,124 @@ module clb_CYINT_CIN (input clk, input [7:0] din, output [7:0] dout);
endmodule
//******************************************************************************
//ACY0
//N5FFMUX
module clb_ACY0_AX (input clk, input [7:0] din, output [7:0] dout);
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
(* LOC="SLICE_X20Y105", BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC="SLICE_X20Y105", KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S({din[7:5], o6}), .CYINIT(1'b0), .CI());
endmodule
module clb_ACY0_O5 (input clk, input [7:0] din, output [7:0] dout);
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
(* LOC="SLICE_X20Y106", BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC="SLICE_X20Y106", KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI({din[3:1], o5}), .S({din[7:5], o6}), .CYINIT(1'b0), .CI());
endmodule
module clb_BCY0_AX (input clk, input [7:0] din, output [7:0] dout);
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X22Y100";
parameter N=-1;
wire lutdo, lutco, lutbo, lutao;
wire lut7bo, lut7ao;
wire lut8o;
reg [3:0] ffds;
wire lutdo5, lutco5, lutbo5, lutao5;
always @(*) begin
s = din[7:4];
s[1] = o6;
/*
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
*/
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[N] = din[6];
end
(* LOC="SLICE_X20Y107", BEL="B6LUT", KEEP, DONT_TOUCH *)
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
.O5(lutdo5),
.O6(lutdo));
(* LOC=LOC, BEL="D5FF" *)
FDPE ffd (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[3]));
(* LOC="SLICE_X20Y107", KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule
module clb_BCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[1] = o6;
di = {din[3:0]};
di[1] = o5;
end
(* LOC="SLICE_X20Y108", BEL="B6LUT", KEEP, DONT_TOUCH *)
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
.O5(lutco5),
.O6(lutco));
(* LOC=LOC, BEL="C5FF" *)
FDPE ffc (
.C(clk),
.Q(dout[2]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[2]));
(* LOC="SLICE_X20Y108", KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
endmodule
module clb_NCY0_AX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
always @(*) begin
s = din[7:4];
s[1] = o6;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
.O5(lutbo5),
.O6(lutbo));
(* LOC=LOC, BEL="B5FF" *)
FDPE ffb (
.C(clk),
.Q(dout[3]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[1]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule
module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[1] = o6;
di = {din[3:0]};
di[1] = o5;
end
(* LOC="SLICE_X20Y108", BEL="B6LUT", KEEP, DONT_TOUCH *)
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC="SLICE_X20Y108", KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
.O5(lutao5),
.O6(lutao));
(* LOC=LOC, BEL="A5FF" *)
FDPE ffa (
.C(clk),
.Q(dout[4]),
.CE(din[0]),
.PRE(din[1]),
//D can only come from O5 or AX
//AX is used by MUXF7:S
.D(ffds[0]));
endmodule

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minitests/clb_n5ffmux/.gitignore vendored Normal file
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@ -0,0 +1,7 @@
/.Xil
/design/
/design.bit
/design.bits
/design.dcp
/usage_statistics_webtalk.*
/vivado*

2
minitests/ncy0/Makefile → minitests/clb_n5ffmux/Makefile
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@ -21,7 +21,7 @@ $(SPECIMENS_OK):
touch $@
clean:
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt
.PHONY: database pushdb clean

20
minitests/clb_n5ffmux/README.txt Normal file
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@ -0,0 +1,20 @@
DFFMUX
30_09 30_54
A 1 0
B 0 1
CFFMUX
30_39 31_45
A 0 1
B 1 0
BFFMUX
30_18 30_19
A 0 1
B 1 0
AFFMUX
30_09 30_55
A 1 0
B 0 1

0
minitests/ncy0/runme.sh → minitests/clb_n5ffmux/runme.sh
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0
minitests/ncy0/runme.tcl → minitests/clb_n5ffmux/runme.tcl
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174
minitests/clb_n5ffmux/top.v Normal file
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@ -0,0 +1,174 @@
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_N5FFMUX # (.LOC("SLICE_X22Y100"), .N(0))
clb_N5FFMUX_0 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y101"), .N(1))
clb_N5FFMUX_1 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y102"), .N(2))
clb_N5FFMUX_2 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y103"), .N(3))
clb_N5FFMUX_3 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
endmodule
module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X22Y100";
parameter N=-1;
parameter DEF_A=1;
wire lutdo, lutco, lutbo, lutao;
wire lut7bo, lut7ao;
wire lut8o;
reg [3:0] ffds;
wire lutdo5, lutco5, lutbo5, lutao5;
//wire lutno5 [3:0] = {lutao5, lutbo5, lutco5, lutdo5};
wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};
always @(*) begin
/*
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
*/
/*
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
*/
if (DEF_A) begin
//Default poliarty A
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[N] = din[6];
end else begin
//Default polarity B
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
ffds[N] = lutno5[N];
end
end
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutdo5),
.O6(lutdo));
(* LOC=LOC, BEL="D5FF" *)
FDPE ffd (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutco5),
.O6(lutco));
(* LOC=LOC, BEL="C5FF" *)
FDPE ffc (
.C(clk),
.Q(dout[2]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutbo5),
.O6(lutbo));
(* LOC=LOC, BEL="B5FF" *)
FDPE ffb (
.C(clk),
.Q(dout[3]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutao5),
.O6(lutao));
(* LOC=LOC, BEL="A5FF" *)
FDPE ffa (
.C(clk),
.Q(dout[4]),
.CE(din[0]),
.PRE(din[1]),
//D can only come from O5 or AX
//AX is used by MUXF7:S
.D(ffds[0]));
endmodule

7
minitests/clb_ncy0/.gitignore vendored Normal file
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@ -0,0 +1,7 @@
/.Xil
/design/
/design.bit
/design.bits
/design.dcp
/usage_statistics_webtalk.*
/vivado*

27
minitests/clb_ncy0/Makefile Normal file
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@ -0,0 +1,27 @@
N := 3
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
all:
bash runme.sh
test -z $(fgrep CRITICAL vivado.log)
segprint -z -D design.bits >design.txt
database: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
pushdb:
${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
$(SPECIMENS_OK):
bash generate.sh $(subst /OK,,$@)
touch $@
clean:
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt
.PHONY: database pushdb clean

0
minitests/ncy0/README.txt → minitests/clb_ncy0/README.txt
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7
minitests/clb_ncy0/runme.sh Executable file
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@ -0,0 +1,7 @@
#!/bin/bash
set -ex
# rm -f vivado*.log vivado*.jou
vivado -mode batch -source runme.tcl
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103

26
minitests/clb_ncy0/runme.tcl Normal file
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@ -0,0 +1,26 @@
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
create_pblock roi
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

0
minitests/ncy0/top.v → minitests/clb_ncy0/top.v
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