Changed folder name for the 'database development process' of the docs and updated the index.rst page accordingly.

Also a few minor changes as requested by @mithro regarding the content itself and rearranged the paragraphs.

Signed-off-by: Davide <davide.toldo@stud.tu-darmstadt.de>

docs/db_dev_process/overview.rst

@@ -1,6 +1,15 @@
 Overview
 =========
 
+SymbiFlow/symbiflow-arch-defs
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+This is where we describe the logical components in a device to VPR.
+
+* VtR stands for `Verilog to Routing <https://verilogtorouting.org/>`_,
+* VPR stands for VtR Place and Route.
+* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys <https://github.com/YosysHQ/yosys>`_ instead of that.
+  
+
 SymbiFlow/prjxray/fuzzers/
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
@@ -16,16 +25,11 @@ By looking at all the resulting specimens, you can correlate which bits in which
 
 Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
 
-SymbiFlow/symbiflow-arch-defs
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-This is where we describe the logical components in a device to VPR.
-VPR stands for place and route software.
-
 SymbiFlow/prjxray/tools/
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
 
-SymbiFlow/minitests/roi_harness
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+SymbiFlow/prjxray/minitests/roi_harness
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).
 

docs/index.rst

@@ -26,4 +26,4 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    :maxdepth: 2
    :caption: Database Development Process
    
-   database development process/overview
+   db_dev_process/overview