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Merge pull request #1334 from tcal-x/master 

Fixes for 100T
This commit is contained in:
litghost 2020-05-18 13:28:04 -07:00 committed by GitHub
parent a4b2a18a9d 9d0499f87a
commit acb6210a76
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 26 additions and 3 deletions
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11
Makefile
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@ -176,9 +176,16 @@ $(foreach PART,$(XRAY_PARTS),$(eval $(call multiple-parts,$(PART))))
db-extras-artix7-parts: $(addprefix db-part-only-,$(ARTIX_PARTS))
# This explicitly sources each settings script as needed so that
# you don't need to worry about manually sourcing the right script before making.
# Some of these commands handle additional parts/packages that are *not* fully bonded.
# For any pin defined in settings/*.sh that is *not* bonded in this part/package,
# override the XRAY_PIN_0X setting below to pick a pin that *is* bonded.
db-extras-artix7-harness:
+XRAY_PIN_00=J13 XRAY_PIN_01=J14 XRAY_PIN_02=K15 XRAY_PIN_03=K16 \
XRAY_PART=xc7a35tftg256-1 XRAY_EQUIV_PART=xc7a50tfgg484-1 $(MAKE) -C fuzzers roi_only
+source settings/artix7.sh && \
XRAY_PIN_00=J13 XRAY_PIN_01=J14 XRAY_PIN_02=K15 XRAY_PIN_03=K16 \
XRAY_PART=xc7a35tftg256-1 XRAY_EQUIV_PART=xc7a50tfgg484-1 \
$(MAKE) -C fuzzers roi_only
+source settings/artix7_100t.sh && \
XRAY_PIN_00=N15 XRAY_PART=xc7a100tcsg324-1 XRAY_EQUIV_PART=xc7a100tfgg676-1 \
$(MAKE) -C fuzzers roi_only

6
settings/artix7.sh
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@ -8,6 +8,10 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAM
export XRAY_EXCLUDE_ROI_TILEGRID=""
# This is used by fuzzers/005-tilegrid/generate_full.py
# (special handling for frame addresses of certain IOIs -- see the script for details).
# This needs to be changed for any new device!
# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST.
export XRAY_IOI3_TILES="LIOI3_X0Y9 RIOI3_X43Y9"
# These settings must remain in sync
@ -19,7 +23,9 @@ export XRAY_ROI_GRID_X2="58"
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="51"
# clock pin
export XRAY_PIN_00="E22"
# data pins
export XRAY_PIN_01="D22"
export XRAY_PIN_02="E21"
export XRAY_PIN_03="D21"

6
settings/artix7_100t.sh
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@ -8,7 +8,11 @@ export XRAY_ROI_TILEGRID="RAMB36_X0Y0:RAMB36_X3Y39 RAMB18_X0Y0:RAMB18_X3Y79 DSP4
export XRAY_EXCLUDE_ROI_TILEGRID=""
export XRAY_IOI3_TILES="RIOI3_X57Y101 LIOI3_X0Y101"
# This is used by fuzzers/005-tilegrid/generate_full.py
# (special handling for frame addresses of certain IOIs -- see the script for details).
# This needs to be changed for any new device!
# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST.
export XRAY_IOI3_TILES="RIOI3_X57Y109 LIOI3_X0Y109"
# clock pin
export XRAY_PIN_00="Y22"

6
settings/artix7_200t.sh
View File

@ -8,9 +8,15 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X163Y249 RAMB18_X0Y0:RAMB18_X8Y99 RAM
export XRAY_EXCLUDE_ROI_TILEGRID=""
# This is used by fuzzers/005-tilegrid/generate_full.py
# (special handling for frame addresses of certain IOIs -- see the script for details).
# This needs to be changed for any new device!
# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST.
export XRAY_IOI3_TILES="RIOI3_X105Y9 LIOI3_X0Y9"
# clock pin
export XRAY_PIN_00="R26"
# data pins
export XRAY_PIN_01="P26"
export XRAY_PIN_02="N26"
export XRAY_PIN_03="M27"