mirror of https://github.com/openXC7/prjxray.git
Merge pull request #668 from litghost/add_missing_cascade_bits
Add CASCOUT_*_ACTIVE bits.
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commit
aa88f68da7
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@ -1,6 +1,7 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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import re
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segmk = Segmaker("design.bits")
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@ -52,12 +53,15 @@ with open("design.txt", "r") as f:
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if pnum == 1 or pdir == 0:
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ignpip.add(pip)
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CASCOUT_RE = re.compile('^BRAM_CASCOUT_ADDR((?:BWR)|(?:ARD))ADDRU([0-9]+)$')
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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srcs = pips_srcs_dsts["srcs"]
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dsts = pips_srcs_dsts["dsts"]
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active_cascout = set()
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for pip, src_dst in pipdata[tile_type].items():
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src, dst = src_dst
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@ -74,11 +78,18 @@ for tile, pips_srcs_dsts in tiledata.items():
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 1)
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elif src_dst[1] not in dsts:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 0)
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m = CASCOUT_RE.match(dst)
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if m and pip in pips:
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active_cascout.add(m.group(1))
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for group in ['BWR', 'ARD']:
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segmk.add_tile_tag(
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tile, 'CASCOUT_{}_ACTIVE'.format(group), group in active_cascout)
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segmk.compile()
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segmk.write()
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