using markdown as package from repository

also moved all documenation sources in `src` directory

Signed-off-by: Alessandro Comodi <[email protected]>

docs/db_dev_process/contributing.md

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-../../CONTRIBUTING.md

docs/db_dev_process/fuzzers/index

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-../../../fuzzers

docs/db_dev_process/fuzzers/index.rst

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-Fuzzers
-=======
-Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
-This is how the contents of the database are generated.
-
-The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target.
-If you picked the IOB (no one is working on that yet), you'd write a design that is implemented in a specific IOB.
-Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin.
-
-A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually.
-
-By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design.
-
-Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
-
-Configurable Logic Blocks (CLB)
--------------------------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *clb*
-
-Block RAM (BRAM)
-----------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *bram*
-
-Input / Output (IOB)
---------------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *iob*
-
-Clocking (CMT, PLL, BUFG, etc)
-------------------------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *clk*
-   *cmt*
-
-Programmable Interconnect Points (PIPs)
----------------------------------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *int*
-   *pip*
-
-Hard Block Fuzzers
-------------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *xadc
-
-Grid and Wire
--------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   tilegrid
-   tileconn
-   ordered_wires
-   get_counts
-   dump_all
-
-Timing
-------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   timing
-
-All Fuzzers
------------
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   *

docs/db_dev_process/minitests/fixedpnr.md

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-../../../minitests/fixedpnr/README.md

docs/db_dev_process/minitests/index

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-../../../minitests

docs/db_dev_process/minitests/index.rst

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-Minitests
-=========
-
-Minitests are experiments to figure out how things work. They allow us to understand how to better write new fuzzers.
-
-.. toctree::
-   :maxdepth: 1
-   :glob:
-
-   clb-bused
-   clb-carry_cin_cyinit
-   clb-configs
-   clb-muxf8
-   clkbuf
-   eccbits
-   fixedpnr
-   index.rst
-   litex
-   lvb_long_mux
-   nodes_wires_list
-   partial_reconfig_flow
-   picorv32-v
-   picorv32-y
-   pip-switchboxes
-   roi_harness
-   srl
-   tiles_wires_pips
-   timing
-   util

docs/db_dev_process/minitests/partial_reconfig_flow.md

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-../../../minitests/partial_reconfig_flow/README.md

docs/db_dev_process/minitests/picorv32-v.md

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-../../../minitests/picorv32-v/README.md

docs/db_dev_process/minitests/picorv32-y.md

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-../../../minitests/picorv32-y/README.md

docs/db_dev_process/minitests/roi_harness.md

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-../../../minitests/roi_harness/README.md

docs/db_dev_process/parts.rst

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-Tools
-=====
-
-`SymbiFlow/prjxray/tools/`
-
-Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.

docs/db_dev_process/readme.md

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-../../README.md