mirror of https://github.com/openXC7/prjxray.git
Merge pull request #578 from litghost/add_zinv_reg_clk
Add remaining RAMB parameters
This commit is contained in:
litghost
GitHub
commit
a8299c84a3
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@ -1,6 +1,6 @@
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N ?= 8
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N ?= 10
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include ../fuzzer.mk
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@ -3,10 +3,16 @@
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27_43 27_44 27_45,BRAM.RAMB18_Y0.READ_WIDTH_B_1
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27_51 27_52 27_53,BRAM.RAMB18_Y0.WRITE_WIDTH_A_1
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27_59 27_60 27_61,BRAM.RAMB18_Y0.WRITE_WIDTH_B_1
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27_96,BRAM.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
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27_124,BRAM.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG
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27_125,BRAM.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG
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# Y1
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27_285 27_284 27_283,BRAM.RAMB18_Y1.READ_WIDTH_A_1
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27_277 27_276 27_275,BRAM.RAMB18_Y1.READ_WIDTH_B_1
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27_269 27_268 27_267,BRAM.RAMB18_Y1.WRITE_WIDTH_A_1
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27_261 27_260 27_259,BRAM.RAMB18_Y1.WRITE_WIDTH_B_1
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27_224,BRAM.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE
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27_196,BRAM.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG
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27_195,BRAM.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG
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@ -1,17 +1,20 @@
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#!/usr/bin/env python3
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import json
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import csv
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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from prjxray import segmaker
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def isinv_tags(segmk, ps, site):
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def isinv_tags(segmk, ps, site, actual_ps):
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# all of these bits are inverted
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ks = [
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('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
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('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
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('IS_REGCLKARDRCLK_INVERTED', 'ZINV_REGCLKARDRCLK'),
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('IS_REGCLKB_INVERTED', 'ZINV_REGCLKB'),
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('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
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('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
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('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
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@ -19,8 +22,33 @@ def isinv_tags(segmk, ps, site):
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('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
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('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
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]
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for param, tagname in ks:
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segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param]))
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# The CLK inverts sometimes are changed during synthesis, resulting
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# in addition inversions. Take this into account.
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if param in actual_ps:
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tag = 1 ^ verilog.parsei(actual_ps[param])
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elif param == 'IS_REGCLKARDRCLK_INVERTED':
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if verilog.parsei(ps['DOA_REG']):
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# When DOA_REG == 1, REGCLKARDRCLK follows the CLKARDCLK setting.
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tag = 1 ^ verilog.parsei(actual_ps['IS_CLKARDCLK_INVERTED'])
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else:
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# When DOA_REG == 0, REGCLKARDRCLK is always inverted.
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tag = 0
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segmk.add_site_tag(site, tagname, tag)
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elif param == 'IS_REGCLKB_INVERTED':
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if verilog.parsei(ps['DOB_REG']):
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# When DOB_REG == 1, REGCLKB follows the CLKBWRCLK setting.
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tag = 1 ^ verilog.parsei(actual_ps['IS_CLKBWRCLK_INVERTED'])
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else:
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# When DOB_REG == 0, REGCLKB is always inverted.
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tag = 0
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else:
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tag = 1 ^ verilog.parsei(ps[param])
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segmk.add_site_tag(site, tagname, tag)
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def bus_tags(segmk, ps, site):
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@ -72,10 +100,29 @@ def write_mode_tags(segmk, ps, site):
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site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
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def write_rstreg_priority(segmk, ps, site):
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for param in ["RSTREG_PRIORITY_A", "RSTREG_PRIORITY_B"]:
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set_val = verilog.unquote(ps[param])
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for opt in ["RSTREG", "REGCE"]:
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segmk.add_site_tag(
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site, "{}_{}".format(param, opt), set_val == opt)
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def write_rdaddr_collision(segmk, ps, site):
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for opt in ["DELAYED_WRITE", "PERFORMANCE"]:
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set_val = verilog.unquote(ps['RDADDR_COLLISION_HWCONFIG'])
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segmk.add_site_tag(
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site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt), set_val == opt)
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def run():
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segmk = Segmaker("design.bits")
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#segmk.set_def_bt('BLOCK_RAM')
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clk_inverts = {}
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with open('design.csv', 'r') as f:
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for params in csv.DictReader(f):
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clk_inverts[params['site']] = params
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print("Loading tags")
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f = open('params.jl', 'r')
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@ -86,10 +133,12 @@ def run():
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assert j['module'] == 'my_RAMB18E1'
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site = verilog.unquote(ps['LOC'])
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isinv_tags(segmk, ps, site)
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isinv_tags(segmk, ps, site, clk_inverts[site])
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bus_tags(segmk, ps, site)
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rw_width_tags(segmk, ps, site)
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write_mode_tags(segmk, ps, site)
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write_rstreg_priority(segmk, ps, site)
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write_rdaddr_collision(segmk, ps, site)
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def bitfilter(frame, bit):
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# rw_width_tags() aliasing interconnect on large widths
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@ -23,3 +23,13 @@ route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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set fp [open "design.csv" "w"]
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puts $fp "site,IS_CLKARDCLK_INVERTED,IS_CLKBWRCLK_INVERTED"
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foreach ram [get_cells "roi/inst_*/ram"] {
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set site [get_sites -of_objects [get_bels -of_objects $ram]]
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set IS_CLKARDCLK_INVERTED [get_property IS_CLKARDCLK_INVERTED $ram]
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set IS_CLKBWRCLK_INVERTED [get_property IS_CLKBWRCLK_INVERTED $ram]
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puts $fp "$site,$IS_CLKARDCLK_INVERTED,$IS_CLKBWRCLK_INVERTED"
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}
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close $fp
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@ -4,7 +4,6 @@ random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.verilog import vrandbit, vrandbits
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import sys
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import json
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@ -37,256 +36,183 @@ def gen_brams():
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yield ('RAMB18E1', site)
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brams = list(gen_brams())
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DUTN = len(brams)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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def place_bram18(site, loci):
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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verilog.top_harness(DIN_N, DOUT_N)
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write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"]
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collisions = ["DELAYED_WRITE", "PERFORMANCE"]
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priorities = ["RSTREG", "REGCE"]
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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# Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
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# also 0 and 36 aren't real sizes
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# Bias choice to 18 as its needed to solve certain bits quickly
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widths = [1, 2, 4, 9, 18, 18, 18, 18]
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': vrandbit(),
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'IS_CLKBWRCLK_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENBWREN_INVERTED': vrandbit(),
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'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
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'IS_RSTRAMB_INVERTED': vrandbit(),
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'IS_RSTREGARSTREG_INVERTED': vrandbit(),
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'IS_RSTREGB_INVERTED': vrandbit(),
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
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'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
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"DOA_REG": vrandbit(),
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"DOB_REG": vrandbit(),
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"SRVAL_A": vrandbits(18),
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"SRVAL_B": vrandbits(18),
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"INIT_A": vrandbits(18),
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"INIT_B": vrandbits(18),
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"READ_WIDTH_A": random.choice(widths),
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"READ_WIDTH_B": random.choice(widths),
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"WRITE_WIDTH_A": random.choice(widths),
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"WRITE_WIDTH_B": random.choice(widths),
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"RDADDR_COLLISION_HWCONFIG": verilog.quote(random.choice(collisions)),
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"RSTREG_PRIORITY_A": verilog.quote(random.choice(priorities)),
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"RSTREG_PRIORITY_B": verilog.quote(random.choice(priorities)),
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}
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for loci, (site_type, site) in enumerate(brams):
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return ('my_RAMB18E1', ports, params)
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def place_bram18():
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"]
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def main():
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brams = list(gen_brams())
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DUTN = len(brams)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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# Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
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# also 0 and 36 aren't real sizes
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# Bias choice to 18 as its needed to solve certain bits quickly
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widths = [1, 2, 4, 9, 18, 18, 18, 18]
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': vrandbit(),
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'IS_CLKBWRCLK_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENBWREN_INVERTED': vrandbit(),
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'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
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'IS_RSTRAMB_INVERTED': vrandbit(),
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'IS_RSTREGARSTREG_INVERTED': vrandbit(),
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'IS_RSTREGB_INVERTED': vrandbit(),
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
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'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
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"DOA_REG": vrandbit(),
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"DOB_REG": vrandbit(),
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"SRVAL_A": vrandbits(18),
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"SRVAL_B": vrandbits(18),
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"INIT_A": vrandbits(18),
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"INIT_B": vrandbits(18),
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"READ_WIDTH_A": random.choice(widths),
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"READ_WIDTH_B": random.choice(widths),
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"WRITE_WIDTH_A": random.choice(widths),
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"WRITE_WIDTH_B": random.choice(widths),
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}
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verilog.top_harness(DIN_N, DOUT_N)
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return ('my_RAMB18E1', ports, params)
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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'''
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def place_bram36():
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': vrandbit(),
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'IS_CLKBWRCLK_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENBWREN_INVERTED': vrandbit(),
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'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
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'IS_RSTRAMB_INVERTED': vrandbit(),
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'IS_RSTREGARSTREG_INVERTED': vrandbit(),
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'IS_RSTREGB_INVERTED': vrandbit(),
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': '"WRITE_FIRST"',
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'WRITE_MODE_B': '"WRITE_FIRST"',
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}
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return ('my_RAMB36E1', ports, params)
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'''
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for loci, (site_type, site) in enumerate(brams):
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modname, ports, params = {
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'RAMB18E1': place_bram18,
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#'RAMBFIFO36E1': place_bram36,
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}[site_type](site, loci)
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modname, ports, params = {
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'RAMB18E1': place_bram18,
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#'RAMBFIFO36E1': place_bram36,
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}[site_type]()
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verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
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verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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# RAMB18E1
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print(
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'''
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module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter IS_CLKARDCLK_INVERTED = 1'b0;
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parameter IS_CLKBWRCLK_INVERTED = 1'b0;
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parameter IS_ENARDEN_INVERTED = 1'b0;
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parameter IS_ENBWREN_INVERTED = 1'b0;
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parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
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parameter IS_RSTRAMB_INVERTED = 1'b0;
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parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
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parameter IS_RSTREGB_INVERTED = 1'b0;
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parameter RAM_MODE = "TDP";
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parameter WRITE_MODE_A = "WRITE_FIRST";
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parameter WRITE_MODE_B = "WRITE_FIRST";
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parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
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parameter RSTREG_PRIORITY_A = "RSTREG";
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parameter RSTREG_PRIORITY_B = "RSTREG";
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parameter DOA_REG = 1'b0;
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parameter DOB_REG = 1'b0;
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parameter SRVAL_A = 18'b0;
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parameter SRVAL_B = 18'b0;
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parameter INIT_A = 18'b0;
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parameter INIT_B = 18'b0;
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parameter READ_WIDTH_A = 0;
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parameter READ_WIDTH_B = 0;
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parameter WRITE_WIDTH_A = 0;
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parameter WRITE_WIDTH_B = 0;
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''')
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print('''\
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(* LOC=LOC *)
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RAMB18E1 #(''')
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for i in range(8):
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print(" .INITP_%02X(256'b0)," % (i, ))
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print('')
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for i in range(0x40):
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print(" .INIT_%02X(256'b0)," % (i, ))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
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.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
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.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
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.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
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.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
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.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
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.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
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.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
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.RAM_MODE(RAM_MODE),
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.WRITE_MODE_A(WRITE_MODE_A),
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.WRITE_MODE_B(WRITE_MODE_B),
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f.close()
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print(
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'''endmodule
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.DOA_REG(DOA_REG),
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.DOB_REG(DOB_REG),
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.SRVAL_A(SRVAL_A),
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.SRVAL_B(SRVAL_B),
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.INIT_A(INIT_A),
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.INIT_B(INIT_B),
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// ---------------------------------------------------------------------
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.READ_WIDTH_A(READ_WIDTH_A),
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.READ_WIDTH_B(READ_WIDTH_B),
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.WRITE_WIDTH_A(WRITE_WIDTH_A),
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.WRITE_WIDTH_B(WRITE_WIDTH_B),
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''')
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.RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG),
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# RAMB18E1
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print(
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'''
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module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter IS_CLKARDCLK_INVERTED = 1'b0;
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parameter IS_CLKBWRCLK_INVERTED = 1'b0;
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parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
parameter DOA_REG = 1'b0;
|
||||
parameter DOB_REG = 1'b0;
|
||||
parameter SRVAL_A = 18'b0;
|
||||
parameter SRVAL_B = 18'b0;
|
||||
parameter INIT_A = 18'b0;
|
||||
parameter INIT_B = 18'b0;
|
||||
|
||||
parameter READ_WIDTH_A = 0;
|
||||
parameter READ_WIDTH_B = 0;
|
||||
parameter WRITE_WIDTH_A = 0;
|
||||
parameter WRITE_WIDTH_B = 0;
|
||||
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
|
||||
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B)
|
||||
) ram (
|
||||
.CLKARDCLK(din[0]),
|
||||
.CLKBWRCLK(din[1]),
|
||||
.ENARDEN(din[2]),
|
||||
.ENBWREN(din[3]),
|
||||
.REGCEAREGCE(din[4]),
|
||||
.REGCEB(din[5]),
|
||||
.RSTRAMARSTRAM(din[6]),
|
||||
.RSTRAMB(din[7]),
|
||||
.RSTREGARSTREG(din[0]),
|
||||
.RSTREGB(din[1]),
|
||||
.ADDRARDADDR(din[2]),
|
||||
.ADDRBWRADDR(din[3]),
|
||||
.DIADI(din[4]),
|
||||
.DIBDI(din[5]),
|
||||
.DIPADIP(din[6]),
|
||||
.DIPBDIP(din[7]),
|
||||
.WEA(din[0]),
|
||||
.WEBWE(din[1]),
|
||||
.DOADO(dout[0]),
|
||||
.DOBDO(dout[1]),
|
||||
.DOPADOP(dout[2]),
|
||||
.DOPBDOP(dout[3]));
|
||||
endmodule
|
||||
''')
|
||||
print('''\
|
||||
(* LOC=LOC *)
|
||||
RAMB18E1 #(''')
|
||||
for i in range(8):
|
||||
print(" .INITP_%02X(256'b0)," % (i, ))
|
||||
print('')
|
||||
for i in range(0x40):
|
||||
print(" .INIT_%02X(256'b0)," % (i, ))
|
||||
print('')
|
||||
print(
|
||||
'''
|
||||
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
|
||||
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
|
||||
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
|
||||
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
|
||||
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
|
||||
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
|
||||
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
|
||||
.RAM_MODE(RAM_MODE),
|
||||
.WRITE_MODE_A(WRITE_MODE_A),
|
||||
.WRITE_MODE_B(WRITE_MODE_B),
|
||||
|
||||
.DOA_REG(DOA_REG),
|
||||
.DOB_REG(DOB_REG),
|
||||
.SRVAL_A(SRVAL_A),
|
||||
.SRVAL_B(SRVAL_B),
|
||||
.INIT_A(INIT_A),
|
||||
.INIT_B(INIT_B),
|
||||
|
||||
.READ_WIDTH_A(READ_WIDTH_A),
|
||||
.READ_WIDTH_B(READ_WIDTH_B),
|
||||
.WRITE_WIDTH_A(WRITE_WIDTH_A),
|
||||
.WRITE_WIDTH_B(WRITE_WIDTH_B)
|
||||
) ram (
|
||||
.CLKARDCLK(din[0]),
|
||||
.CLKBWRCLK(din[1]),
|
||||
.ENARDEN(din[2]),
|
||||
.ENBWREN(din[3]),
|
||||
.REGCEAREGCE(din[4]),
|
||||
.REGCEB(din[5]),
|
||||
.RSTRAMARSTRAM(din[6]),
|
||||
.RSTRAMB(din[7]),
|
||||
.RSTREGARSTREG(din[0]),
|
||||
.RSTREGB(din[1]),
|
||||
.ADDRARDADDR(din[2]),
|
||||
.ADDRBWRADDR(din[3]),
|
||||
.DIADI(din[4]),
|
||||
.DIBDI(din[5]),
|
||||
.DIPADIP(din[6]),
|
||||
.DIPBDIP(din[7]),
|
||||
.WEA(din[0]),
|
||||
.WEBWE(din[1]),
|
||||
.DOADO(dout[0]),
|
||||
.DOBDO(dout[1]),
|
||||
.DOPADOP(dout[2]),
|
||||
.DOPBDOP(dout[3]));
|
||||
endmodule
|
||||
''')
|
||||
|
||||
print(
|
||||
'''
|
||||
|
||||
module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
|
||||
parameter LOC = "";
|
||||
parameter IS_CLKARDCLK_INVERTED = 1'b0;
|
||||
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
|
||||
parameter IS_ENARDEN_INVERTED = 1'b0;
|
||||
parameter IS_ENBWREN_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
||||
parameter IS_RSTRAMB_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
|
||||
parameter IS_RSTREGB_INVERTED = 1'b0;
|
||||
parameter RAM_MODE = "TDP";
|
||||
parameter WRITE_MODE_A = "WRITE_FIRST";
|
||||
parameter WRITE_MODE_B = "WRITE_FIRST";
|
||||
|
||||
''')
|
||||
print('')
|
||||
print('''\
|
||||
(* LOC=LOC *)
|
||||
RAMB36E1 #(''')
|
||||
for i in range(16):
|
||||
print(" .INITP_%02X(256'b0)," % (i, ))
|
||||
print('')
|
||||
for i in range(0x80):
|
||||
print(" .INIT_%02X(256'b0)," % (i, ))
|
||||
print('')
|
||||
print(
|
||||
'''
|
||||
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
|
||||
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
|
||||
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
|
||||
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
|
||||
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
|
||||
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
|
||||
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
|
||||
.RAM_MODE(RAM_MODE),
|
||||
.WRITE_MODE_A(WRITE_MODE_A),
|
||||
.WRITE_MODE_B(WRITE_MODE_B)
|
||||
) ram (
|
||||
.CLKARDCLK(din[0]),
|
||||
.CLKBWRCLK(din[1]),
|
||||
.ENARDEN(din[2]),
|
||||
.ENBWREN(din[3]),
|
||||
.REGCEAREGCE(din[4]),
|
||||
.REGCEB(din[5]),
|
||||
.RSTRAMARSTRAM(din[6]),
|
||||
.RSTRAMB(din[7]),
|
||||
.RSTREGARSTREG(din[0]),
|
||||
.RSTREGB(din[1]),
|
||||
.ADDRARDADDR(din[2]),
|
||||
.ADDRBWRADDR(din[3]),
|
||||
.DIADI(din[4]),
|
||||
.DIBDI(din[5]),
|
||||
.DIPADIP(din[6]),
|
||||
.DIPBDIP(din[7]),
|
||||
.WEA(din[0]),
|
||||
.WEBWE(din[1]),
|
||||
.DOADO(dout[0]),
|
||||
.DOBDO(dout[1]),
|
||||
.DOPADOP(dout[2]),
|
||||
.DOPBDOP(dout[3]));
|
||||
endmodule
|
||||
''')
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
# read/write width is relatively slow to resolve
|
||||
# Even slower with multi bit masks...
|
||||
N ?= 2
|
||||
|
||||
include ../fuzzer.mk
|
||||
|
||||
database: build/segbits_bramx.db
|
||||
|
||||
build/segbits_bramx.rdb: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
|
||||
|
||||
build/segbits_bramx.db: build/segbits_bramx.rdb
|
||||
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
|
||||
${XRAY_MASKMERGE} build/mask_bramx.db $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
|
||||
|
||||
pushdb:
|
||||
${XRAY_MERGEDB} bram_l build/segbits_bramx.db
|
||||
${XRAY_MERGEDB} bram_r build/segbits_bramx.db
|
||||
${XRAY_MERGEDB} mask_bram_l build/mask_bramx.db
|
||||
${XRAY_MERGEDB} mask_bram_r build/mask_bramx.db
|
||||
|
||||
.PHONY: database pushdb
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# Y0
|
||||
27_188,BRAM.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER
|
||||
|
||||
# Y1
|
||||
27_187,BRAM.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import json
|
||||
|
||||
from prjxray.segmaker import Segmaker
|
||||
|
||||
|
||||
def write_ram_ext_tags(segmk, tile_param):
|
||||
for param in ["RAM_EXTENSION_A", "RAM_EXTENSION_B"]:
|
||||
set_val = tile_param[param]
|
||||
for opt in ["LOWER"]:
|
||||
segmk.add_site_tag(
|
||||
tile_param['site'], "{}_{}".format(param, opt), set_val == opt)
|
||||
segmk.add_site_tag(
|
||||
tile_param['site'], "{}_NONE_OR_UPPER".format(param, opt),
|
||||
set_val != "LOWER")
|
||||
|
||||
|
||||
def main():
|
||||
segmk = Segmaker("design.bits")
|
||||
|
||||
print("Loading tags")
|
||||
with open('params.json') as f:
|
||||
params = json.load(f)
|
||||
|
||||
for tile_param in params:
|
||||
write_ram_ext_tags(segmk, tile_param)
|
||||
|
||||
segmk.add_site_tag(
|
||||
tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
|
||||
segmk.add_site_tag(
|
||||
tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
|
||||
|
||||
segmk.compile()
|
||||
segmk.write()
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDCN-137}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-191}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-192}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-193}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-194}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-94}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {AVAL-95}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {PDCN-1576}]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
import os
|
||||
import random
|
||||
import json
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray import verilog
|
||||
|
||||
|
||||
def gen_bram36():
|
||||
for tile_name, site_name, _site_type in util.get_roi().gen_sites(
|
||||
['RAMBFIFO36E1']):
|
||||
yield tile_name, site_name
|
||||
|
||||
|
||||
RAM_EXTENSION_OPTS = [
|
||||
"NONE",
|
||||
"LOWER",
|
||||
"UPPER",
|
||||
]
|
||||
|
||||
|
||||
def main():
|
||||
print('''
|
||||
module top();
|
||||
''')
|
||||
|
||||
params = []
|
||||
for tile_name, site_name in gen_bram36():
|
||||
ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
|
||||
ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
|
||||
en_ecc_read = random.randint(0, 1)
|
||||
en_ecc_write = random.randint(0, 1)
|
||||
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
RAMB36E1 #(
|
||||
.READ_WIDTH_A(1),
|
||||
.WRITE_WIDTH_A(1),
|
||||
.READ_WIDTH_B(1),
|
||||
.WRITE_WIDTH_B(1),
|
||||
.RAM_EXTENSION_A({ram_extension_a}),
|
||||
.RAM_EXTENSION_B({ram_extension_b}),
|
||||
.EN_ECC_READ({en_ecc_read}),
|
||||
.EN_ECC_WRITE({en_ecc_write})
|
||||
) bram_{site} (
|
||||
.CLKARDCLK(),
|
||||
.CLKBWRCLK(),
|
||||
.ENARDEN(),
|
||||
.ENBWREN(),
|
||||
.REGCEAREGCE(),
|
||||
.REGCEB(),
|
||||
.RSTRAMARSTRAM(),
|
||||
.RSTRAMB(),
|
||||
.RSTREGARSTREG(),
|
||||
.RSTREGB(),
|
||||
.ADDRARDADDR(),
|
||||
.ADDRBWRADDR(),
|
||||
.DIADI(),
|
||||
.DIBDI(),
|
||||
.DIPADIP(),
|
||||
.DIPBDIP(),
|
||||
.WEA(),
|
||||
.WEBWE(),
|
||||
.DOADO(),
|
||||
.DOBDO(),
|
||||
.DOPADOP(),
|
||||
.DOPBDOP());
|
||||
'''.format(
|
||||
site=site_name,
|
||||
ram_extension_a=verilog.quote(ram_extension_a),
|
||||
ram_extension_b=verilog.quote(ram_extension_b),
|
||||
en_ecc_read=en_ecc_read,
|
||||
en_ecc_write=en_ecc_write,
|
||||
))
|
||||
|
||||
params.append(
|
||||
{
|
||||
'tile': tile_name,
|
||||
'site': site_name,
|
||||
'RAM_EXTENSION_A': ram_extension_a,
|
||||
'RAM_EXTENSION_B': ram_extension_b,
|
||||
'EN_ECC_READ': en_ecc_read,
|
||||
'EN_ECC_WRITE': en_ecc_write,
|
||||
})
|
||||
|
||||
print("endmodule")
|
||||
|
||||
with open('params.json', 'w') as f:
|
||||
json.dump(params, f, indent=2)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Loading…
Reference in New Issue