mirror of https://github.com/openXC7/prjxray.git
roi_harness: basys3 support, separate top.v into harness and ROI .v files
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
d587030ea5
commit
a39e1bca78
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@ -1 +1,3 @@
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export XRAY_PART=xc7a35tcsg324-1
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export XRAY_PART=xc7a35tcsg324-1
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export XRAY_PINCFG=ARTY_A7_SWBUT
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@ -0,0 +1,4 @@
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# XC7A35T-1CPG236C
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export XRAY_PART=xc7a35tcpg236-1
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export XRAY_PINCFG=BASYS3_SWBUT
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@ -0,0 +1,8 @@
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`ifndef DIN_N
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`define DIN_N 8
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`endif
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`ifndef DOUT_N
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`define DOUT_N 8
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`endif
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@ -0,0 +1,49 @@
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//See README and tcl for more info
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`include "defines.v"
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O());
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(1'b0),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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@ -43,6 +43,7 @@ source ../../utils/utils.tcl
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create_project -force -part $::env(XRAY_PART) design design
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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read_verilog top.v
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read_verilog roi_base.v
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# added flatten_hierarchy
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# added flatten_hierarchy
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# dout_shr was getting folded into the pblock
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# dout_shr was getting folded into the pblock
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# synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
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# synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
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@ -53,6 +54,10 @@ array set net2pin [list]
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# Create pin assignments based on what we are targetting
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# Create pin assignments based on what we are targetting
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set part "$::env(XRAY_PART)"
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set part "$::env(XRAY_PART)"
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set pincfg ""
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if { [info exists ::env(XRAY_PINCFG) ] } {
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set pincfg "$::env(XRAY_PINCFG)"
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}
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# A50T I/O Bank 16 sequential layout
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# A50T I/O Bank 16 sequential layout
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if {$part eq "xc7a50tfgg484-1"} {
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if {$part eq "xc7a50tfgg484-1"} {
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# Partial list, expand as needed
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# Partial list, expand as needed
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@ -79,52 +84,83 @@ if {$part eq "xc7a50tfgg484-1"} {
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}
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}
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# Arty A7 switch, button, and LED
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# Arty A7 switch, button, and LED
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} elseif {$part eq "xc7a35tcsg324-1"} {
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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if {$pincfg eq "ARTY_A7_SWBUT"} {
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# 4 switches then 4 buttons
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set sw_but "A8 C11 C10 A10 D9 C9 B9 B8"
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# 4 switches then 4 buttons
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# 4 LEDs then 4 RGB LEDs (green only)
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set sw_but "A8 C11 C10 A10 D9 C9 B9 B8"
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set leds "H5 J5 T9 T10 F6 J4 J2 H6"
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# 4 LEDs then 4 RGB LEDs (green only)
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set leds "H5 J5 T9 T10 F6 J4 J2 H6"
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# 100 MHz CLK onboard
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# 100 MHz CLK onboard
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set pin "E3"
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set pin "E3"
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set net2pin(clk) $pin
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set net2pin(clk) $pin
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# DIN
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $sw_but $i]
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set pin [lindex $sw_but $i]
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set net2pin(din[$i]) $pin
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set net2pin(din[$i]) $pin
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}
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$pincfg eq "ARTY_A7_PMOD"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# CLK on Pmod JA
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set pin [lindex $pmod_ja 0]
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set net2pin(clk) $pin
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# DIN on Pmod JB
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set net2pin(din[$i]) $pin
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}
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# DOUT on Pmod JC
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set net2pin(dout[$i]) $pin
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}
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} else {
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error "Unsupported config $pincfg"
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}
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}
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# Arty A7 switch, button, and LED
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} elseif {$part eq "xc7a35tcpg236-1"} {
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if {$pincfg eq "BASYS3_SWBUT"} {
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# https://raw.githubusercontent.com/Digilent/digilent-xdc/master/Basys-3-Master.xdc
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# DOUT
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# Slide switches
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set sws "V17 V16 W16 W17 W15 V15 W14 W13 V2 T3 T2 R3 W2 U1 T1 R2"
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set pin [lindex $leds $i]
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set leds "U16 E19 U19 V19 W18 U15 U14 V14 V13 V3 W3 U3 P3 N3 P1 L1"
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set net2pin(dout[$i]) $pin
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}
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# Arty A7 pmod
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# Disabled per above
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# CLK on Pmod JA
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# 100 MHz CLK onboard
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set pin [lindex $pmod_ja 0]
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set pin "W5"
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set net2pin(clk) $pin
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set net2pin(clk) $pin
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# DIN on Pmod JB
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# DIN
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for {set i 0} {$i < $DIN_N} {incr i} {
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set pin [lindex $sws $i]
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set net2pin(din[$i]) $pin
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set net2pin(din[$i]) $pin
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}
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}
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# DOUT on Pmod JC
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# DOUT
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for {set i 0} {$i < $DOUT_N} {incr i} {
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set pin [lindex $leds $i]
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set net2pin(dout[$i]) $pin
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set net2pin(dout[$i]) $pin
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}
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}
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} else {
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error "Unsupported config $pincfg"
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}
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} else {
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} else {
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error "Unsupported part $part"
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error "Pins: unsupported part $part"
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}
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}
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# Now actually apply the pin definitions
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# Now actually apply the pin definitions
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@ -338,8 +374,11 @@ if {1} {
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} elseif {$part eq "xc7a35tcsg324-1"} {
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} elseif {$part eq "xc7a35tcsg324-1"} {
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set node "INT_L_X10Y${y}/SW6BEG0"
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set node "INT_L_X10Y${y}/SW6BEG0"
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route_via2 "roi/dout[$i]" "$node"
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route_via2 "roi/dout[$i]" "$node"
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} elseif {$part eq "xc7a35tcpg236-1"} {
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set node "INT_L_X10Y${y}/SW6BEG0"
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route_via2 "roi/dout[$i]" "$node"
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} else {
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} else {
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error "Unsupported part $part"
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error "Routing: unsupported part $part"
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}
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}
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# XXX: only care about right ports on Arty
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# XXX: only care about right ports on Arty
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} else {
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} else {
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@ -358,5 +397,6 @@ puts "routing design"
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route_design
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route_design
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write_checkpoint -force design.dcp
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write_checkpoint -force design.dcp
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set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
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write_bitstream -force design.bit
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write_bitstream -force design.bit
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@ -1,12 +1,6 @@
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//See README and tcl for more info
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//See README and tcl for more info
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`ifndef DIN_N
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`include "defines.v"
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`define DIN_N 4
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`endif
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`ifndef DOUT_N
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`define DOUT_N 4
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`endif
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module top(input wire clk,
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module top(input wire clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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@ -18,48 +12,3 @@ module top(input wire clk,
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.din(din), .dout(dout));
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.din(din), .dout(dout));
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endmodule
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endmodule
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = 4;
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parameter DOUT_N = 4;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O());
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(1'b0),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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