iob: Enhance fuzzer with bits for SLEW and DRIVE for LVCMOS25

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak 2019-02-06 10:57:33 +01:00
parent e2b88458e8
commit a11abfd972
4 changed files with 51 additions and 21 deletions

View File

@ -1,2 +1,12 @@
38_92 39_93 38_94,LIOB33.IOB_Y0.PULLTYPE.PULLDOWN
38_118 38_126 39_117 39_119 39_125 39_127,LIOB33.IOB_Y0.LVCMOS25.DRIVE.12
38_106 38_110 39_105 39_109,LIOB33.IOB_Y0.SLEW.FAST
39_33 38_34 39_35,LIOB33.IOB_Y1.PULLTYPE.PULLDOWN
38_00 38_02 38_08 38_10 39_01 39_09,LIOB33.IOB_Y1.LVCMOS25.DRIVE.12
38_18 38_22 39_17 39_21,LIOB33.IOB_Y1.SLEW.FAST
38_92 39_93 38_94,RIOB33.IOB_Y0.PULLTYPE.PULLDOWN
38_118 38_126 39_117 39_119 39_125 39_127,RIOB33.IOB_Y0.LVCMOS25.DRIVE.12
38_106 38_110 39_105 39_109,RIOB33.IOB_Y0.SLEW.FAST
39_33 38_34 39_35,RIOB33.IOB_Y1.PULLTYPE.PULLDOWN
38_00 38_02 38_08 38_10 39_01 39_09,RIOB33.IOB_Y1.LVCMOS25.DRIVE.12
38_18 38_22 39_17 39_21,RIOB33.IOB_Y1.SLEW.FAST

View File

@ -7,7 +7,7 @@ segmk = Segmaker("design.bits")
print("Loading tags")
'''
port,site,tile,pin,val
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
@ -15,19 +15,35 @@ f = open('design.csv', 'r')
f.readline()
for l in f:
l = l.strip()
port, site, tile, pin, val = l.split(',')
port, site, tile, pin, iostandard, slew, drive, pulltype = l.split(',')
'''
LVCMOS25
SLEW 38_82 38_86 39_81 39_85
SLOW X X X X
FAST
DRIVE 38_64 38_66 38_72 38_74 39_65 39_73
4 X X X
8 X
12
16 X X X
PULLTYPE 28 29 30
NONE X
KEEPER X X
PULLDOWN
PULLUP X X
'''
if val == "":
val = "NONE"
if pulltype == "":
pulltype = "NONE"
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.", ("NONE", "KEEPER", "PULLDOWN", "PULLUP"),
"PULLDOWN", val)
"PULLDOWN", pulltype)
segmaker.add_site_group_zero(
segmk, site, iostandard + ".DRIVE.", ("4", "8", "12", "16"), "12",
drive)
segmaker.add_site_group_zero(
segmk, site, "SLEW.", ("SLOW", "FAST"), "FAST", slew)
segmk.compile()
segmk.write()

View File

@ -32,7 +32,7 @@ proc loc_pins {} {
set io_pin_sites [make_io_pin_sites]
set fp [open "design.csv" w]
puts $fp "port,site,tile,pin,val"
puts $fp "port,site,tile,pin,iostandard,slew,drive,pulltype"
puts "Looping"
for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
@ -53,20 +53,27 @@ proc loc_pins {} {
set tile [get_tiles -of_objects $site]
set pin [dict get $io_pin_sites $site]
set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port
set iostandard_val "LVCMOS25"
set_property -dict "PACKAGE_PIN $pin IOSTANDARD $iostandard_val" $port
# list_property isn't working (maybe due to empty?)
# set keys [list_property_value PULLTYPE $port]
# NONE placeholder for ""
set keys "NONE PULLUP PULLDOWN KEEPER"
set val [randsample_list 1 $keys]
if { $val == "NONE" } {
set val ""
set pulltype "NONE PULLUP PULLDOWN KEEPER"
set pulltype_val [randsample_list 1 $pulltype]
if { $pulltype_val == "NONE" } {
set pulltype_val ""
}
set_property PULLTYPE $pulltype_val $port
set_property PULLTYPE $val $port
# puts "IOB $port $site $tile $pin $val"
puts $fp "$port,$site,$tile,$pin,$val"
if {$io == "input"} continue
set drive "4 8 12 16"
set drive_val [lindex $drive [expr {$idx % 4}]]
set_property DRIVE $drive_val $port
set slew "SLOW FAST"
set slew_val [lindex $slew [expr {($idx + ($idx / 4)) % 2}]]
set_property SLEW $slew_val $port
puts $fp "$port,$site,$tile,$pin,$iostandard_val,$slew_val,$drive_val,$pulltype_val"
}
close $fp
}

View File

@ -76,10 +76,7 @@ def run():
assign_o(rand_site(), 'do[0]')
# Now assign the rest randomly
while len(remain_sites()):
if random.randint(0, 1):
assign_i(rand_site(), 'di[%u]' % DIN_N)
else:
assign_o(rand_site(), 'do[%u]' % DOUT_N)
assign_o(rand_site(), 'do[%u]' % DOUT_N)
write_pins(ports)