mirror of https://github.com/openXC7/prjxray.git
005-tilegrid/gtx_int_interface fuzzer works
Signed-off-by: Hans Baier <foss@hans-baier.de>
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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N ?= 8
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GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1b --dword 0 --dbit 4"
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include ../fuzzaddr/common.mk
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SEGBITS=$(BUILD_DIR)/segbits_tilegrid.tdb
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$(SEGBITS): $(SPECIMENS_OK)
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# multiple bits match for the changes, but all of those except the ones with addresses ending with 0x9b are known
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# and not related to GTX_INT_INTERFACE
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${XRAY_SEGMATCH} -c 6 -o $(BUILD_DIR)/segbits_tilegrid.tdb $$(find $(BUILD_DIR) -name "segdata_tilegrid.txt")
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tr ' ' '\n' < $(SEGBITS) | grep -E 'GTX|9B' | paste -d " " - - > $(SEGBITS).tmp
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mv -fv $(SEGBITS).tmp $(SEGBITS)
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc parse_csv {} {
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set fp [open "params.csv"]
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set file_data [read $fp]
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close $fp
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set file_data [split $file_data "\n"]
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set params_map [dict create]
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set is_first_line true
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foreach line $file_data {
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if { $is_first_line } {
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set is_first_line false
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continue
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}
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# Skip empty lines
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if { $line == "" } {
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continue
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}
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set parts [split $line ","]
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dict lappend params_map [lindex $parts 2] [lindex $parts 1]
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}
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return $params_map
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}
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proc route_through_delay {} {
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set params_map [parse_csv]
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dict for { key value } $params_map {
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if { $value == 0 } {
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continue
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}
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set net_name "QPLLLOCKEN_$key"
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set net [get_nets $net_name]
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set wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTX_INT_INTERFACE*" && NAME =~ "*IMUX_OUT24*"}]
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set wire_parts [split $wire "/"]
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set gtx_int_tile [lindex $wire_parts 0]
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set node [get_nodes -of_object [get_tiles $gtx_int_tile] -filter { NAME =~ "*DELAY24" }]
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route_design -unroute -nets $net
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puts "Attempting to route net $net through $node."
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route_via $net [list $node]
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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# Disable MMCM frequency etc sanity checks
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set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
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place_design
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route_design
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route_through_delay
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os
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import re
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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from prjxray.grid_types import GridLoc
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GTX_INT_Y_RE = re.compile("GTX_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
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def get_gtx_int_tile(clock_region, grid):
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for tile_name in sorted(grid.tiles()):
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if not tile_name.startswith("GTX_INT_INTERFACE"):
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continue
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loc = grid.loc_of_tilename(tile_name)
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left_gridinfo = grid.gridinfo_at_loc(
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GridLoc(loc.grid_x - 1, loc.grid_y))
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right_gridinfo = grid.gridinfo_at_loc(
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GridLoc(loc.grid_x + 1, loc.grid_y))
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if left_gridinfo.tile_type in ["INT_L", "INT_R"]:
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cmt = left_gridinfo.clock_region
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elif right_gridinfo.tile_type in ["INT_L", "INT_R"]:
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cmt = right_gridinfo.clock_region
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else:
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assert False
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gridinfo = grid.gridinfo_at_loc(loc)
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m = GTX_INT_Y_RE.match(tile_name)
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assert m
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int_y = int(m.group(1))
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if clock_region == cmt and int_y % 50 == 26:
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return tile_name
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def gen_sites():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['GTXE2_COMMON']:
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gtx_int_tile = get_gtx_int_tile(gridinfo.clock_region, grid)
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yield gtx_int_tile, site_name
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def write_params(params):
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pinstr = 'tile,val,site\n'
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for tile, (site, val) in sorted(params.items()):
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pinstr += '%s,%s,%s\n' % (tile, val, site)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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params = {}
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sites = list(gen_sites())
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for gtx_int_tile, site_name in sites:
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isone = random.randint(0, 1)
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params[gtx_int_tile] = (site_name, isone)
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print(
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'''
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wire QPLLLOCKEN_{site};
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(* KEEP, DONT_TOUCH *)
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LUT1 lut_{site} (.O(QPLLLOCKEN_{site}));
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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GTXE2_COMMON gtxe2_common_{site} (
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.QPLLLOCKEN(QPLLLOCKEN_{site})
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);'''.format(site=site_name))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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