005-tilegrid/util.py: Added functionalities to local util

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

fuzzers/005-tilegrid/util.py

@@ -5,6 +5,99 @@ from prjxray import util
 Local utils script to hold shared code of the 005-tilegrid fuzzer scripts
 '''
 
+def check_frames(addrlist):
+    frames = set()
+    for addrstr in addrlist:
+        frame = parse_addr(addrstr, get_base_frame=True)
+        frames.add(frame)
+    assert len(frames) == 1, "More than one base address"
+
+
+def parse_addr(line, only_frame=False, get_base_frame=False):
+    # 00020027_003_03
+    line = line.split("_")
+    frame = int(line[0], 16)
+    wordidx = int(line[1], 10)
+    bitidx = int(line[2], 10)
+
+    if get_base_frame:
+        delta = frame % 128
+        frame -= delta
+        return frame
+
+    return frame, wordidx, bitidx
+
+
+def propagate_up_INT(grid_x, grid_y, database, tiles_by_grid, wordbase):
+    for i in range(50):
+        grid_y -= 1
+        loc = (grid_x, grid_y)
+        if loc not in tiles_by_grid:
+            continue
+
+        tile = database[tiles_by_grid[loc]]
+
+        if wordbase == 50:
+            wordbase += 1
+        else:
+            wordbase += 2
+        yield tile, wordbase
+
+
+def add_baseaddr(tile_baseaddrs, tile_name, baseaddr, verbose=False):
+    bt = util.addr2btype(baseaddr)
+    tile_baseaddr = tile_baseaddrs.setdefault(tile_name, {})
+    if bt in tile_baseaddr:
+        # actually lets just fail these, better to remove at tcl level to speed up processing
+        assert 0, 'duplicate base address'
+        assert tile_baseaddr[bt] == [baseaddr, 0]
+    else:
+        tile_baseaddr[bt] = [baseaddr, 0]
+    verbose and print(
+        "baseaddr: %s.%s @ %s.0x%08x" %
+        (tile["name"], site_name, bt, baseaddr))
+
+
+def get_entry(tile_type, block_type):
+    """
+    FIXME: review IOB
+        # IOB
+        # design_IOB_X0Y100.delta:+bit_00020027_000_29
+        # design_IOB_X0Y104.delta:+bit_00020027_008_29
+        # design_IOB_X0Y112.delta:+bit_00020027_024_29
+        # design_IOB_X0Y120.delta:+bit_00020027_040_29
+        # design_IOB_X0Y128.delta:+bit_00020027_057_29
+        # design_IOB_X0Y136.delta:+bit_00020027_073_29
+        # design_IOB_X0Y144.delta:+bit_00020027_089_29
+        # $XRAY_BLOCKWIDTH design_IOB_X0Y100.bit |grep 00020000
+        # 0x00020000: 0x2A (42)
+        ("RIOI3", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOI3", "CLB_IO_CLK"): (42, 2, 4),
+        ("RIOI3_SING", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOI3_SING", "CLB_IO_CLK"): (42, 2, 4),
+        ("RIOI3_TBYTESRC", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOI3_TBYTESRC", "CLB_IO_CLK"): (42, 2, 4),
+        ("RIOI3_TBYTETERM", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOI3_TBYTETERM", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOB33", "CLB_IO_CLK"): (42, 2, 4),
+        ("RIOB33", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOB33", "CLB_IO_CLK"): (42, 2, 4),
+        ("RIOB33_SING", "CLB_IO_CLK"): (42, 2, 4),
+        ("LIOB33_SING", "CLB_IO_CLK"): (42, 2, 4),
+    """
+    return {
+        # (tile_type, block_type): (frames, words, height)
+        ("CLBLL", "CLB_IO_CLK"): (36, 2, 2),
+        ("CLBLM", "CLB_IO_CLK"): (36, 2, 2),
+        ("HCLK", "CLB_IO_CLK"): (26, 1, 1),
+        ("INT", "CLB_IO_CLK"): (28, 2, 2),
+        ("BRAM", "CLB_IO_CLK"): (28, 10, None),
+        ("BRAM", "BLOCK_RAM"): (128, 10, None),
+        ("DSP", "CLB_IO_CLK"): (28, 2, 10),
+        ("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
+        ("BRAM_INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),
+    }.get((tile_type, block_type), None)
+
 
 def add_tile_bits(
         tile_name,
@@ -21,7 +114,6 @@ def add_tile_bits(
     Notes on multiple block types:
     https://github.com/SymbiFlow/prjxray/issues/145
     '''
-
     bits = tile_db['bits']
     block_type = util.addr2btype(baseaddr)
 
@@ -43,7 +135,6 @@ def add_tile_bits(
             tile_name, block["offset"], offset)
         assert block["words"] == words
         return
-
     block = bits.setdefault(block_type, {})
 
     # FDRI address