mirror of https://github.com/openXC7/prjxray.git
first running (but not working) fuzzer for CFG_CENTER_MID
This commit is contained in:
Hans Baier
parent
a9b160e4c5
commit
98d0733c42
|
|
@ -0,0 +1,61 @@
|
|||
# Copyright (C) 2017-2023 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
export FUZDIR=$(shell pwd)
|
||||
PIP_TYPE?=cfg_center
|
||||
PIPLIST_TCL=$(FUZDIR)/cfg_pip_list.tcl
|
||||
|
||||
BUILD_DIR = build
|
||||
RUN_OK = run.ok
|
||||
|
||||
TODO_RE=".*"
|
||||
|
||||
MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(PIP_TYPE) --re $(TODO_RE) --sides "mid"
|
||||
N = 1
|
||||
|
||||
SEGMATCH_FLAGS=-c 186
|
||||
|
||||
A_PIPLIST=cfg_center.txt
|
||||
|
||||
CHECK_ARGS= --zero-entries --timeout-iters 2
|
||||
|
||||
include ../pip_loop.mk
|
||||
|
||||
#$(BUILD_DIR)/segbits_cfg_center_top.rdb: $(SPECIMENS_OK)
|
||||
# ${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_cfg_center_top.rdb \
|
||||
# $(shell find $(BUILD_DIR) -name segdata_cfg_center_top.txt)
|
||||
|
||||
$(BUILD_DIR)/segbits_cfg_center_mid.rdb: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_cfg_center_mid.rdb \
|
||||
$(shell find $(BUILD_DIR) -name segdata_cfg_center_mid.txt)
|
||||
|
||||
RDBS = $(BUILD_DIR)/segbits_cfg_center_mid.rdb # $(BUILD_DIR)/segbits_cfg_center_top.rdb
|
||||
|
||||
database: ${RDBS}
|
||||
# ${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
|
||||
# --seg-fn-in $(BUILD_DIR)/segbits_cfg_center_top.rdb \
|
||||
# --seg-fn-out $(BUILD_DIR)/segbits_cfg_center_top.db
|
||||
${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
|
||||
--seg-fn-in $(BUILD_DIR)/segbits_cfg_center_mid.rdb \
|
||||
--seg-fn-out $(BUILD_DIR)/segbits_cfg_center_mid.db
|
||||
|
||||
# Keep a copy to track iter progress
|
||||
# cp $(BUILD_DIR)/segbits_cfg_center_top.rdb $(BUILD_DIR)/$(ITER)/segbits_cfg_center_top.rdb
|
||||
# cp $(BUILD_DIR)/segbits_cfg_center_top.db $(BUILD_DIR)/$(ITER)/segbits_cfg_center_top.db
|
||||
cp $(BUILD_DIR)/segbits_cfg_center_mid.rdb $(BUILD_DIR)/$(ITER)/segbits_cfg_center_mid.rdb
|
||||
cp $(BUILD_DIR)/segbits_cfg_center_mid.db $(BUILD_DIR)/$(ITER)/segbits_cfg_center_mid.db
|
||||
|
||||
# Clobber existing .db to eliminate potential conflicts
|
||||
cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE}
|
||||
# XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} cfg_center_top $(BUILD_DIR)/segbits_cfg_center_top.db
|
||||
XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} cfg_center_mid $(BUILD_DIR)/segbits_cfg_center_mid.db
|
||||
|
||||
pushdb: database
|
||||
# ${XRAY_MERGEDB} cfg_center_top $(BUILD_DIR)/segbits_cfg_center_top.db
|
||||
${XRAY_MERGEDB} cfg_center_mid $(BUILD_DIR)/segbits_cfg_center_mid.db
|
||||
|
||||
.PHONY: database pushdb run clean
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
# Copyright (C) 2017-2023 The Project X-Ray Authors
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
proc print_tile_pips {tile_type filename} {
|
||||
set fp [open $filename w]
|
||||
set pips [dict create]
|
||||
foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] {
|
||||
puts "got tile: $tile"
|
||||
foreach pip [lsort [get_pips -of_objects $tile]] {
|
||||
puts "got pip: $pip"
|
||||
set src [get_wires -uphill -of_objects $pip]
|
||||
set dst [get_wires -downhill -of_objects $pip]
|
||||
puts "$src ==> $dst"
|
||||
|
||||
# Skip pips with disconnected nodes
|
||||
set src_node [get_nodes -of_objects $src]
|
||||
|
||||
puts "src_node: $src_node"
|
||||
|
||||
if { $src_node == {} } {
|
||||
puts "source node no good"
|
||||
continue
|
||||
}
|
||||
|
||||
set dst_node [get_nodes -of_objects $dst]
|
||||
puts "dst_node: $dst_node"
|
||||
if { $dst_node == {} } {
|
||||
puts "dst_node node no good"
|
||||
continue
|
||||
}
|
||||
|
||||
if { true } {
|
||||
set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
|
||||
if ![dict exists $pips $pip_string] {
|
||||
puts $fp $pip_string
|
||||
dict set pips $pip_string 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
set_property design_mode PinPlanning [current_fileset]
|
||||
open_io_design -name io_1
|
||||
|
||||
print_tile_pips CFG_CENTER_MID cfg_center_mid.txt
|
||||
#print_tile_pips CFG_CENTER_TOP cfg_center_top.txt
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2017-2023 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
|
||||
from prjxray.segmaker import Segmaker
|
||||
import os
|
||||
import os.path
|
||||
|
||||
|
||||
def bitfilter(frame, word):
|
||||
#if frame not in [26, 27]:
|
||||
# return False
|
||||
|
||||
return True
|
||||
|
||||
|
||||
def read_pip_data(pipfile, pipdata, tile_ports):
|
||||
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
|
||||
'cfg_center', pipfile)) as f:
|
||||
for l in f:
|
||||
tile_type, dst, src = l.strip().split('.')
|
||||
if tile_type not in pipdata:
|
||||
pipdata[tile_type] = []
|
||||
tile_ports[tile_type] = set()
|
||||
|
||||
pipdata[tile_type].append((src, dst))
|
||||
tile_ports[tile_type].add(src)
|
||||
tile_ports[tile_type].add(dst)
|
||||
|
||||
|
||||
def main():
|
||||
segmk = Segmaker("design.bits")
|
||||
|
||||
tiledata = {}
|
||||
pipdata = {}
|
||||
ignpip = set()
|
||||
tile_ports = {}
|
||||
|
||||
read_pip_data('cfg_center_mid.txt', pipdata, tile_ports)
|
||||
#read_pip_data('cfg_center_top.txt', pipdata, tile_ports)
|
||||
|
||||
print("Loading tags from design.txt.")
|
||||
with open("design.txt", "r") as f:
|
||||
for line in f:
|
||||
tile, pip, src, dst, pnum, pdir = line.split()
|
||||
|
||||
if not tile.startswith('CFG'):
|
||||
continue
|
||||
|
||||
pip_prefix, _ = pip.split(".")
|
||||
tile_from_pip, tile_type = pip_prefix.split('/')
|
||||
assert tile == tile_from_pip
|
||||
_, src = src.split("/")
|
||||
_, dst = dst.split("/")
|
||||
pnum = int(pnum)
|
||||
pdir = int(pdir)
|
||||
|
||||
if tile not in tiledata:
|
||||
tiledata[tile] = {
|
||||
"type": tile_type,
|
||||
"pips": set(),
|
||||
"srcs": set(),
|
||||
"dsts": set()
|
||||
}
|
||||
|
||||
tiledata[tile]["pips"].add((src, dst))
|
||||
tiledata[tile]["srcs"].add(src)
|
||||
tiledata[tile]["dsts"].add(dst)
|
||||
|
||||
if pdir == 0:
|
||||
tiledata[tile]["srcs"].add(dst)
|
||||
tiledata[tile]["dsts"].add(src)
|
||||
|
||||
for tile, pips_srcs_dsts in tiledata.items():
|
||||
tile_type = pips_srcs_dsts["type"]
|
||||
# we only do CFG_CENTER_MID for now
|
||||
if tile_type == "CFG_CENTER_TOP":
|
||||
continue
|
||||
pips = pips_srcs_dsts["pips"]
|
||||
|
||||
for src, dst in pipdata[tile_type]:
|
||||
if (src, dst) in ignpip:
|
||||
pass
|
||||
elif (src, dst) in pips:
|
||||
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
|
||||
else:
|
||||
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
|
||||
|
||||
segmk.compile(bitfilter=bitfilter)
|
||||
segmk.write()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
# Copyright (C) 2017-2023 The Project X-Ray Authors
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
source "$::env(XRAY_DIR)/utils/utils.tcl"
|
||||
|
||||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-21}]
|
||||
set_property IS_ENABLED 0 [get_drc_checks {REQP-25}]
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
|
||||
|
||||
place_design -directive Quick
|
||||
route_design -directive Quick
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_pip_txtdata design.txt
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2017-2023 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
|
||||
ports = {
|
||||
"EFUSE_USR": [
|
||||
# ("EFUSEUSR", 32), # Output
|
||||
],
|
||||
"DNA_PORT": [
|
||||
("CLK", 1),
|
||||
("DIN", 1),
|
||||
# ("DOUT", 1), # Output
|
||||
("READ", 1),
|
||||
("SHIFT", 1),
|
||||
],
|
||||
"ICAPE2": [
|
||||
("CLK", 1),
|
||||
("CSIB", 1),
|
||||
("I", 32),
|
||||
# ("O", 32), # Output
|
||||
("RDWRB", 1),
|
||||
],
|
||||
"BSCANE2": [
|
||||
# ("CAPTURE", 1), # Output
|
||||
# ("DRCK", 1), # Output
|
||||
# ("RESET", 1), # Output
|
||||
# ("RUNTEST", 1), # Output
|
||||
# ("SEL", 1), # Output
|
||||
# ("SHIFT", 1), # Output
|
||||
# ("TCK", 1), # Output
|
||||
# ("TDI", 1), # Output
|
||||
("TDO", 1),
|
||||
# ("TMS", 1), # Output
|
||||
# ("UPDATE", 1), # Output
|
||||
],
|
||||
"DCIRESET": [
|
||||
# ("LOCKED", 1), # Output
|
||||
("RST", 1),
|
||||
],
|
||||
"CAPTUREE2": [
|
||||
("CAP", 1),
|
||||
("CLK", 1),
|
||||
],
|
||||
"STARTUPE2": [
|
||||
# ("CFGCLK", 1), # Output
|
||||
# ("CFGMCLK", 1), # Output
|
||||
("CLK", 1),
|
||||
# ("EOS", 1),
|
||||
("GSR", 1),
|
||||
("GTS", 1),
|
||||
("KEYCLEARB", 1),
|
||||
("PACK", 1),
|
||||
# ("PREQ", 1), # Output
|
||||
("USRCCLKO", 1),
|
||||
("USRCCLKTS", 1),
|
||||
("USRDONEO", 1),
|
||||
("USRDONETS", 1),
|
||||
],
|
||||
"FRAME_ECCE2": [
|
||||
# ("CRCERROR", 1), # Output
|
||||
# ("ECCERROR", 1), # Output
|
||||
# ("ECCERRORSINGLE", 1), # Output
|
||||
# ("FAR", 26), # Output
|
||||
# ("SYNBIT", 5), # Output
|
||||
# ("SYNDROME", 13), # Output
|
||||
# ("SYNDROMEVAL ID", 1), # Output
|
||||
# ("SYNWORD", 7), # Output
|
||||
],
|
||||
"USR_ACCESSE2": [
|
||||
# ("CFGCLK", 1), # Output
|
||||
# ("DATA", 32), # Output
|
||||
# ("DATAVALID", 1), # Output
|
||||
],
|
||||
}
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2017-2023 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
import os
|
||||
import random
|
||||
import math
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.lut_maker import LutMaker
|
||||
from prjxray.db import Database
|
||||
|
||||
from ports import ports
|
||||
|
||||
|
||||
def print_site(ports, luts, site, site_type):
|
||||
verilog_ports = ""
|
||||
verilog_wires = ""
|
||||
|
||||
params = ""
|
||||
if site_type == "BSCANE2":
|
||||
chain_no = int(site.split("Y")[1]) + 1
|
||||
params = f"#(.JTAG_CHAIN({chain_no}))"
|
||||
|
||||
for port, width in ports:
|
||||
verilog_ports += """
|
||||
.{port}({port}_{site}),""".format(
|
||||
port=port, site=site)
|
||||
verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site)
|
||||
|
||||
for idx in range(0, width):
|
||||
rand = random.random()
|
||||
|
||||
if rand < 0.45:
|
||||
source = "1'b0"
|
||||
elif rand < 0.9:
|
||||
source = "1'b1"
|
||||
else:
|
||||
source = luts.get_next_output_net()
|
||||
|
||||
verilog_wires += "assign {}_{}[{}] = {};\n".format(
|
||||
port, site, idx, source)
|
||||
|
||||
verilog_wires += "\n"
|
||||
|
||||
verilog_ports = verilog_ports.rstrip(",")
|
||||
|
||||
print(
|
||||
"""
|
||||
{wires}
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
{site_type} {params} {site}_instance (
|
||||
{ports}
|
||||
);""".format(
|
||||
wires=verilog_wires,
|
||||
ports=verilog_ports,
|
||||
site=site,
|
||||
params=params,
|
||||
site_type=site_type))
|
||||
|
||||
|
||||
def main():
|
||||
db = Database(util.get_db_root(), util.get_part())
|
||||
grid = db.grid()
|
||||
|
||||
luts = LutMaker()
|
||||
|
||||
def gen_sites(desired_site_type):
|
||||
desired_site_type = desired_site_type.replace("E2", "")
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == desired_site_type:
|
||||
yield tile_name, site
|
||||
|
||||
print('''
|
||||
module top();
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy();
|
||||
''')
|
||||
|
||||
for site_type in [
|
||||
#"EFUSE_USR",
|
||||
#"DNA_PORT",
|
||||
"ICAPE2",
|
||||
"BSCANE2",
|
||||
"DCIRESET",
|
||||
"CAPTUREE2",
|
||||
"STARTUPE2",
|
||||
"FRAME_ECCE2",
|
||||
"USR_ACCESSE2"]:
|
||||
for _, site in gen_sites(site_type):
|
||||
print_site(ports[site_type], luts, site, site_type)
|
||||
|
||||
for l in luts.create_wires_and_luts():
|
||||
print(l)
|
||||
|
||||
print('endmodule')
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue