mirror of https://github.com/openXC7/prjxray.git
litghost
GitHub
commit
9811626594
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@ -14,6 +14,7 @@ TILEGRID_TDB_DEPENDENCIES += fifo_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += cfg_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clk_hrow/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clk_bufg/build/segbits_tilegrid.tdb
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GENERATE_FULL_ARGS=
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ifeq (${XRAY_DATABASE}, zynq7)
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@ -100,6 +101,9 @@ orphan_int_column/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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clk_hrow/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd clk_hrow && $(MAKE)
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clk_bufg/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd clk_bufg && $(MAKE)
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build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
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python3 add_tdb.py \
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--fn-in build/basicdb/tilegrid.json \
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@ -134,6 +138,7 @@ clean:
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cd cfg_int && $(MAKE) clean
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cd orphan_int_column && $(MAKE) clean
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cd clk_hrow && $(MAKE) clean
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cd clk_bufg && $(MAKE) clean
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.PHONY: database pushdb clean run
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@ -85,6 +85,7 @@ def run(fn_in, fn_out, verbose=False):
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("clb/build/segbits_tilegrid.tdb", 36, 2),
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("dsp/build/segbits_tilegrid.tdb", 28, 10),
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("clk_hrow/build/segbits_tilegrid.tdb", 30, 7),
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("clk_bufg/build/segbits_tilegrid.tdb", 30, 8),
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("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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@ -1,19 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -1,19 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -0,0 +1,4 @@
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N ?= 5
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GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 1B"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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generate_top
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@ -0,0 +1,62 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in grid.tiles():
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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sites = []
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for site, site_type in gridinfo.sites.items():
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if site_type == 'BUFGCTRL':
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sites.append(site)
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if sites:
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yield tile_name, sorted(sites)
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def write_params(params):
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pinstr = 'tile,val,site\n'
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for tile, (site, val) in sorted(params.items()):
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pinstr += '%s,%s,%s\n' % (tile, val, site)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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params = {}
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sites = list(gen_sites())
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for (tile_name, sites), isone in zip(sites,
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util.gen_fuzz_states(len(sites))):
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site_name = sites[0]
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params[tile_name] = (site_name, isone)
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFGCTRL #(
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.INIT_OUT({isone})
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) buf_{site} (
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.CE0(1),
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.S0(1)
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);
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'''.format(
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site=site_name,
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isone=isone,
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))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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@ -1,21 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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#set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -1,19 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -1,19 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -1,4 +1,5 @@
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#!/usr/bin/env python3
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import copy
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import json
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from utils import xjson
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'''
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@ -210,6 +211,40 @@ def propagate_INT_bits_in_column(database, tiles_by_grid):
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tile = database[tile_name]
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def propagate_rebuf(database, tiles_by_grid):
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""" Writing a fuzzer for the CLK_BUFG_REBUF tiles is hard, so propigate from CLK_HROW tiles.
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In the clock column, there is a CLK_BUFG_REBUF above and below the CLK_HROW
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tile. Each clock column appears to use the same offsets, so propigate
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the base address and frame count, and update the offset and word count.
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"""
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for tile_name in sorted(database.keys()):
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tile = database[tile_name]
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if tile['type'] not in ['CLK_HROW_BOT_R', 'CLK_HROW_TOP_R']:
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continue
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rebuf_below = tiles_by_grid[(tile['grid_x'], tile['grid_y'] - 12)]
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assert database[rebuf_below]['type'] == 'CLK_BUFG_REBUF', database[
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rebuf_below]['type']
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rebuf_above = tiles_by_grid[(tile['grid_x'], tile['grid_y'] + 13)]
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assert database[rebuf_above]['type'] == 'CLK_BUFG_REBUF', database[
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rebuf_below]['type']
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assert database[tile_name]['bits']['CLB_IO_CLK'][
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'offset'] == 47, database[tile_name]['bits']['CLB_IO_CLK']
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database[rebuf_below]['bits'] = copy.deepcopy(
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database[tile_name]['bits'])
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database[rebuf_below]['bits']['CLB_IO_CLK']['offset'] = 73
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database[rebuf_below]['bits']['CLB_IO_CLK']['words'] = 4
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database[rebuf_above]['bits'] = copy.deepcopy(
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database[tile_name]['bits'])
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database[rebuf_above]['bits']['CLB_IO_CLK']['offset'] = 24
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database[rebuf_above]['bits']['CLB_IO_CLK']['words'] = 4
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def run(json_in_fn, json_out_fn, verbose=False):
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# Load input files
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database = json.load(open(json_in_fn, "r"))
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@ -217,6 +252,7 @@ def run(json_in_fn, json_out_fn, verbose=False):
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propagate_INT_lr_bits(database, tiles_by_grid, verbose=verbose)
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propagate_INT_bits_in_column(database, tiles_by_grid)
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propagate_rebuf(database, tiles_by_grid)
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# Save
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xjson.pprint(open(json_out_fn, "w"), database)
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@ -1,19 +1,3 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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generate_top
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@ -4,8 +4,8 @@ PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
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MAKETODO_FLAGS=--no-l --pip-type clk_hrow_bot --seg-type clk_hrow_bot --re "[^\.]+\.CLK_HROW_CK_MUX_OUT_"
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N = 50
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# These PIPs all appear to be either a 0 or 2 bit solution.
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SEGMATCH_FLAGS=-m 20 -M 45 -c 2
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# These PIPs all appear to be either a 1 bit solutions.
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SEGMATCH_FLAGS=-c 1
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SPECIMENS_DEPS=build/cmt_regions.csv
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A_PIPLIST=clk_hrow_bot_r.txt
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@ -18,7 +18,7 @@ build/cmt_regions.csv: output_cmt.tcl
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_hrow.rdb \
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_clk_hrow.rdb \
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$(addsuffix /segdata_clk_hrow_top_r.txt,$(SPECIMENS)) \
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$(addsuffix /segdata_clk_hrow_bot_r.txt,$(SPECIMENS))
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@ -9,6 +9,9 @@ def main():
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table = clk_table.get_clk_table()
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print("Loading tags from design.txt.")
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active_gclks = {}
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active_clks = {}
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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@ -44,6 +47,30 @@ def main():
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segmk.add_tile_tag(
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tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
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if tile not in active_clks:
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active_clks[tile] = set()
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active_clks[tile].add(src)
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if 'GCLK' in src:
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if src not in active_gclks:
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active_gclks[src] = set()
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active_gclks[src].add(tile)
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tiles = sorted(active_clks.keys())
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for tile in active_clks:
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for src in table:
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if 'GCLK' not in src:
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active = src in active_clks[tile]
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
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else:
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if src not in active_gclks:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 0)
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elif tile in active_gclks[src]:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
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segmk.compile()
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segmk.write()
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@ -11,6 +11,7 @@ def main():
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args = parser.parse_args()
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output_features = []
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hrow_outs = {}
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tile = None
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with open(args.in_segbit) as f:
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@ -19,6 +20,11 @@ def main():
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feature = parts[0]
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bits = ' '.join(parts[1:])
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# No post-processing on _ACTIVE bits.
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if feature.endswith('_ACTIVE'):
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output_features.append(l.strip())
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continue
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tile1, dst, src = feature.split('.')
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if tile is None:
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tile = tile1
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@ -53,6 +59,9 @@ def main():
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table = clk_table.get_clk_table()
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with open(args.out_segbit, 'w') as f:
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for l in output_features:
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print(l, file=f)
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for dst in sorted(hrow_outs):
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for src in sorted(piplists[dst]):
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if src not in table:
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@ -0,0 +1,22 @@
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N ?= 50
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include ../fuzzer.mk
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database: build/segbits_clk_bufg.db
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build/segbits_clk_bufg.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_clk_bufg.rdb $(addsuffix /segdata_clk_bufg_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_bufg_bot_r.txt,$(SPECIMENS))
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build/segbits_clk_bufg.db: build/segbits_clk_bufg.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_clk_bufg.rdb \
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--seg-fn-out build/segbits_clk_bufg.db
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${XRAY_MASKMERGE} build/mask_clk_bufg.db $(addsuffix /segdata_clk_bufg_top_r.txt,$(SPECIMENS)) $(addsuffix /segdata_clk_bufg_bot_r.txt,$(SPECIMENS))
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pushdb: database
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${XRAY_MERGEDB} clk_bufg_bot_r build/segbits_clk_bufg.db
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${XRAY_MERGEDB} clk_bufg_top_r build/segbits_clk_bufg.db
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${XRAY_MERGEDB} mask_clk_bufg_bot_r build/mask_clk_bufg.db
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${XRAY_MERGEDB} mask_clk_bufg_top_r build/mask_clk_bufg.db
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|
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.PHONY: database pushdb
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|
|
@ -0,0 +1,61 @@
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#!/usr/bin/env python3
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||||
|
||||
import json
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||||
|
||||
from prjxray.segmaker import Segmaker
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|
||||
|
||||
def main():
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segmk = Segmaker("design.bits")
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|
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print("Loading tags")
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with open('params.json') as f:
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params = json.load(f)
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|
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for row in params:
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base_name = 'BUFGCTRL_X{}Y{}'.format(row['x'], row['y'])
|
||||
|
||||
segmk.add_site_tag(
|
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row['site'], '{}.IN_USE'.format(base_name), row['IN_USE'])
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|
||||
if not row['IN_USE']:
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continue
|
||||
|
||||
for param in (
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||||
'INIT_OUT',
|
||||
'IS_IGNORE0_INVERTED',
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||||
'IS_IGNORE1_INVERTED',
|
||||
):
|
||||
segmk.add_site_tag(
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||||
row['site'], '{}.{}'.format(base_name, param), row[param])
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||||
|
||||
if row['connect0'] and row['connect1']:
|
||||
for param in ('PRESELECT_I0', ):
|
||||
segmk.add_site_tag(
|
||||
row['site'], '{}.Z{}'.format(base_name, param),
|
||||
1 ^ row[param])
|
||||
|
||||
for param in ('PRESELECT_I1', ):
|
||||
segmk.add_site_tag(
|
||||
row['site'], '{}.{}'.format(base_name, param), row[param])
|
||||
|
||||
if row['connect0']:
|
||||
for param, tag in (('IS_CE0_INVERTED', 'ZINV_CE0'),
|
||||
('IS_S0_INVERTED', 'ZINV_S0')):
|
||||
segmk.add_site_tag(
|
||||
row['site'], '{}.{}'.format(base_name, tag),
|
||||
1 ^ row[param])
|
||||
|
||||
if row['connect1']:
|
||||
for param, tag in (('IS_CE1_INVERTED', 'ZINV_CE1'),
|
||||
('IS_S1_INVERTED', 'ZINV_S1')):
|
||||
segmk.add_site_tag(
|
||||
row['site'], '{}.{}'.format(base_name, tag),
|
||||
1 ^ row[param])
|
||||
|
||||
segmk.compile()
|
||||
segmk.write()
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
import json
|
||||
import os
|
||||
import random
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.db import Database
|
||||
|
||||
|
||||
def gen_sites():
|
||||
xy_fun = util.create_xy_fun('BUFGCTRL_')
|
||||
db = Database(util.get_db_root())
|
||||
grid = db.grid()
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
sites = []
|
||||
|
||||
xs = []
|
||||
ys = []
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == 'BUFGCTRL':
|
||||
x, y = xy_fun(site)
|
||||
xs.append(x)
|
||||
ys.append(y)
|
||||
|
||||
sites.append((site, x, y))
|
||||
|
||||
if sites:
|
||||
yield tile_name, min(xs), min(ys), sorted(sites)
|
||||
|
||||
|
||||
def main():
|
||||
print('''
|
||||
module top();
|
||||
''')
|
||||
|
||||
params_list = []
|
||||
for tile_name, x_min, y_min, sites in gen_sites():
|
||||
|
||||
for site, x, y in sites:
|
||||
params = {}
|
||||
params['tile'] = tile_name
|
||||
params['site'] = site
|
||||
params['x'] = x - x_min
|
||||
params['y'] = y - y_min
|
||||
params['IN_USE'] = random.random() > .1
|
||||
|
||||
if params['IN_USE']:
|
||||
params['INIT_OUT'] = random.randint(0, 1)
|
||||
params['IS_CE0_INVERTED'] = random.randint(0, 1)
|
||||
params['IS_CE1_INVERTED'] = random.randint(0, 1)
|
||||
params['IS_S0_INVERTED'] = random.randint(0, 1)
|
||||
params['IS_S1_INVERTED'] = random.randint(0, 1)
|
||||
params['IS_IGNORE0_INVERTED'] = random.randint(0, 1)
|
||||
params['IS_IGNORE1_INVERTED'] = random.randint(0, 1)
|
||||
params['PRESELECT_I0'] = 0
|
||||
params['PRESELECT_I1'] = 0
|
||||
|
||||
params['connect0'] = random.randint(0, 1)
|
||||
|
||||
if params['connect0']:
|
||||
params['connect1'] = random.randint(0, 1)
|
||||
else:
|
||||
params['connect1'] = 1
|
||||
|
||||
if params['connect0'] and params['connect1']:
|
||||
params['PRESELECT_I0'] = random.randint(0, 1)
|
||||
if not params['PRESELECT_I0']:
|
||||
params['PRESELECT_I1'] = random.randint(0, 1)
|
||||
else:
|
||||
params['PRESELECT_I1'] = 0
|
||||
|
||||
params['connections'] = """
|
||||
.CE0(ce0_{site}),
|
||||
.S0(s0_{site}),
|
||||
.CE1(ce1_{site}),
|
||||
.S1(s1_{site})
|
||||
""".format(site=site)
|
||||
elif params['connect0']:
|
||||
params['connections'] = """
|
||||
.CE0(ce0_{site}),
|
||||
.S0(s0_{site})
|
||||
""".format(site=site)
|
||||
elif params['connect1']:
|
||||
params['connections'] = """
|
||||
.CE1(ce1_{site}),
|
||||
.S1(s1_{site})
|
||||
""".format(site=site)
|
||||
|
||||
print(
|
||||
'''
|
||||
wire ce0_{site};
|
||||
wire s0_{site};
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 l0_{site} (
|
||||
.O(ce0_{site})
|
||||
);
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 l1_{site} (
|
||||
.O(s0_{site})
|
||||
);
|
||||
|
||||
wire ce1_{site};
|
||||
wire s1_{site};
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 l2_{site} (
|
||||
.O(ce1_{site})
|
||||
);
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 l3_{site} (
|
||||
.O(s1_{site})
|
||||
);
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFGCTRL #(
|
||||
.INIT_OUT({INIT_OUT}),
|
||||
.PRESELECT_I0({PRESELECT_I0}),
|
||||
.PRESELECT_I1({PRESELECT_I1}),
|
||||
.IS_CE0_INVERTED({IS_CE0_INVERTED}),
|
||||
.IS_CE1_INVERTED({IS_CE1_INVERTED}),
|
||||
.IS_S0_INVERTED({IS_S0_INVERTED}),
|
||||
.IS_S1_INVERTED({IS_S1_INVERTED}),
|
||||
.IS_IGNORE0_INVERTED({IS_IGNORE0_INVERTED}),
|
||||
.IS_IGNORE1_INVERTED({IS_IGNORE1_INVERTED})
|
||||
) buf_{site} (
|
||||
{connections}
|
||||
);
|
||||
'''.format(**params))
|
||||
|
||||
params_list.append(params)
|
||||
|
||||
print("endmodule")
|
||||
|
||||
with open('params.json', 'w') as f:
|
||||
json.dump(params_list, f, indent=2)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
N ?= 25
|
||||
|
||||
include ../fuzzer.mk
|
||||
|
||||
database: build/segbits_clk_bufg_rebuf.db
|
||||
|
||||
build/segbits_clk_bufg_rebuf.rdb: $(SPECIMENS_OK)
|
||||
${XRAY_SEGMATCH} -c 1 -o build/segbits_clk_bufg_rebuf.rdb \
|
||||
$(addsuffix /segdata_clk_bufg_rebuf.txt,$(SPECIMENS))
|
||||
|
||||
build/segbits_clk_bufg_rebuf.db: build/segbits_clk_bufg_rebuf.rdb
|
||||
${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
|
||||
--seg-fn-in build/segbits_clk_bufg_rebuf.rdb \
|
||||
--seg-fn-out build/segbits_clk_bufg_rebuf.db
|
||||
${XRAY_MASKMERGE} build/mask_clk_bufg_rebuf.db \
|
||||
$(addsuffix /segdata_clk_bufg_rebuf.txt,$(SPECIMENS))
|
||||
|
||||
pushdb: database
|
||||
${XRAY_MERGEDB} clk_bufg_rebuf build/segbits_clk_bufg_rebuf.db
|
||||
${XRAY_MERGEDB} mask_clk_bufg_rebuf build/mask_clk_bufg_rebuf.db
|
||||
|
||||
.PHONY: database pushdb
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from prjxray.segmaker import Segmaker
|
||||
from prjxray.db import Database
|
||||
from prjxray.util import get_db_root
|
||||
import re
|
||||
|
||||
REBUF_GCLK = re.compile('^CLK_BUFG_REBUF_R_CK_GCLK([0-9]+)_BOT$')
|
||||
|
||||
GCLKS = 32
|
||||
|
||||
|
||||
def gclk_of_wire(wire):
|
||||
m = REBUF_GCLK.match(wire)
|
||||
assert m, wire
|
||||
return int(m.group(1))
|
||||
|
||||
|
||||
class ClockColumn(object):
|
||||
def __init__(self, db_root):
|
||||
db = Database(db_root)
|
||||
grid = db.grid()
|
||||
|
||||
tiles_in_gclk_columns = []
|
||||
self.gclk_columns = {}
|
||||
|
||||
for tile in grid.tiles():
|
||||
gridinfo = grid.gridinfo_at_tilename(tile)
|
||||
|
||||
if gridinfo.tile_type != 'CLK_BUFG_REBUF':
|
||||
continue
|
||||
|
||||
loc = grid.loc_of_tilename(tile)
|
||||
|
||||
tiles_in_gclk_columns.append((loc.grid_y, tile))
|
||||
|
||||
_, self.tiles_in_gclk_columns = zip(
|
||||
*sorted(tiles_in_gclk_columns, key=lambda x: x[0]))
|
||||
|
||||
# Initially all GCLK lines are idle. GCLK lines only exist between
|
||||
#CLK_BUFG_REBUF tiles, hence len-1.
|
||||
for gclk in range(GCLKS):
|
||||
self.gclk_columns[gclk] = [
|
||||
False for _ in range(len(self.tiles_in_gclk_columns) - 1)
|
||||
]
|
||||
|
||||
def enable_rebuf(self, tile, wire):
|
||||
# Find which REBUF is being activated.
|
||||
rebuf_idx = self.tiles_in_gclk_columns.index(tile)
|
||||
assert rebuf_idx != -1, tile
|
||||
|
||||
gclk = gclk_of_wire(wire)
|
||||
|
||||
self.gclk_columns[gclk][rebuf_idx] = True
|
||||
self.gclk_columns[gclk][rebuf_idx - 1] = True
|
||||
|
||||
def yield_rebuf_state(self):
|
||||
""" Yields tile_name, gclk, bool if active above tile, bool if active below tile """
|
||||
for idx, tile in enumerate(self.tiles_in_gclk_columns):
|
||||
for gclk in range(GCLKS):
|
||||
active_below = False
|
||||
active_above = False
|
||||
|
||||
if idx > 0:
|
||||
active_below = self.gclk_columns[gclk][idx - 1]
|
||||
|
||||
if idx < len(self.gclk_columns[gclk]):
|
||||
active_above = self.gclk_columns[gclk][idx]
|
||||
|
||||
yield tile, gclk, active_below, active_above
|
||||
|
||||
|
||||
def main():
|
||||
db_root = get_db_root()
|
||||
|
||||
clock_column = ClockColumn(db_root)
|
||||
|
||||
segmk = Segmaker("design.bits")
|
||||
|
||||
print("Loading tags from design.txt.")
|
||||
|
||||
with open("route.txt", "r") as f:
|
||||
for line in f:
|
||||
if 'CLK_BUFG_REBUF' not in line:
|
||||
continue
|
||||
|
||||
parts = line.replace('{', '').replace('}', '').strip().replace(
|
||||
'\t', ' ').split(' ')
|
||||
dst = parts[0]
|
||||
pip = parts[3]
|
||||
|
||||
tile_from_pip, pip = pip.split('/')
|
||||
|
||||
if 'CLK_BUFG_REBUF' not in tile_from_pip:
|
||||
continue
|
||||
|
||||
tile_type, pip = pip.split('.')
|
||||
assert tile_type == 'CLK_BUFG_REBUF'
|
||||
|
||||
wire_a, wire_b = pip.split('<<->>')
|
||||
|
||||
tile_from_wire, dst = dst.split('/')
|
||||
|
||||
assert dst == wire_a
|
||||
|
||||
if tile_from_wire == tile_from_pip:
|
||||
b_to_a = wire_a == dst
|
||||
a_to_b = not b_to_a
|
||||
else:
|
||||
b_to_a = wire_a != dst
|
||||
a_to_b = not b_to_a
|
||||
|
||||
segmk.add_tile_tag(
|
||||
tile_from_pip, '{}.{}'.format(wire_a, wire_b), b_to_a)
|
||||
segmk.add_tile_tag(
|
||||
tile_from_pip, '{}.{}'.format(wire_b, wire_a), a_to_b)
|
||||
|
||||
clock_column.enable_rebuf(tile_from_pip, wire_a)
|
||||
|
||||
for tile, gclk, active_below, active_above in clock_column.yield_rebuf_state(
|
||||
):
|
||||
segmk.add_tile_tag(
|
||||
tile, 'GCLK{}_ENABLE_ABOVE'.format(gclk), active_above)
|
||||
segmk.add_tile_tag(
|
||||
tile, 'GCLK{}_ENABLE_BELOW'.format(gclk), active_below)
|
||||
|
||||
segmk.compile()
|
||||
segmk.write(allow_empty=True)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
source "$::env(XRAY_DIR)/utils/utils.tcl"
|
||||
|
||||
proc write_pip_txtdata {filename} {
|
||||
puts "FUZ([pwd]): Writing $filename."
|
||||
set fp [open $filename w]
|
||||
set nets [get_nets -hierarchical]
|
||||
set nnets [llength $nets]
|
||||
set neti 0
|
||||
foreach net $nets {
|
||||
incr neti
|
||||
if {($neti % 100) == 0 } {
|
||||
puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
|
||||
}
|
||||
foreach pip [get_pips -of_objects $net] {
|
||||
set tile [get_tiles -of_objects $pip]
|
||||
set src_wire [get_wires -uphill -of_objects $pip]
|
||||
set dst_wire [get_wires -downhill -of_objects $pip]
|
||||
set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
|
||||
set dir_prop [get_property IS_DIRECTIONAL $pip]
|
||||
puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
|
||||
}
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc write_route_data {filename} {
|
||||
set fp [open $filename w]
|
||||
foreach net [get_nets -hierarchical] {
|
||||
puts $fp "Net $net route:"
|
||||
puts $fp [report_route_status -of_objects $net -return_string]
|
||||
puts $fp ""
|
||||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
proc run {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
write_route_data route.txt
|
||||
write_pip_txtdata pips.txt
|
||||
}
|
||||
|
||||
run
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
import os
|
||||
import itertools
|
||||
import re
|
||||
import random
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.db import Database
|
||||
|
||||
XY_RE = re.compile('^BUFHCE_X([0-9]+)Y([0-9]+)$')
|
||||
BUFGCTRL_XY_RE = re.compile('^BUFGCTRL_X([0-9]+)Y([0-9]+)$')
|
||||
"""
|
||||
BUFHCE's can be driven from:
|
||||
|
||||
MMCME2_ADV
|
||||
BUFHCE
|
||||
PLLE2_ADV
|
||||
BUFGCTRL
|
||||
"""
|
||||
|
||||
|
||||
def get_xy(s):
|
||||
m = BUFGCTRL_XY_RE.match(s)
|
||||
x = int(m.group(1))
|
||||
y = int(m.group(2))
|
||||
return x, y
|
||||
|
||||
|
||||
def gen_sites(desired_site_type):
|
||||
db = Database(util.get_db_root())
|
||||
grid = db.grid()
|
||||
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == desired_site_type:
|
||||
yield site
|
||||
|
||||
|
||||
def gen_bufhce_sites():
|
||||
db = Database(util.get_db_root())
|
||||
grid = db.grid()
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
sites = []
|
||||
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == 'BUFHCE':
|
||||
sites.append(site)
|
||||
|
||||
if sites:
|
||||
yield tile_name, set(sites)
|
||||
|
||||
|
||||
def main():
|
||||
print('''
|
||||
module top();
|
||||
''')
|
||||
|
||||
gclks = []
|
||||
for site in sorted(gen_sites("BUFGCTRL"), key=get_xy):
|
||||
wire_name = 'clk_{}'.format(site)
|
||||
gclks.append(wire_name)
|
||||
|
||||
print(
|
||||
"""
|
||||
wire {wire_name};
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFG bufg_{site} (
|
||||
.O({wire_name})
|
||||
);
|
||||
""".format(
|
||||
site=site,
|
||||
wire_name=wire_name,
|
||||
))
|
||||
|
||||
bufhce_sites = list(gen_bufhce_sites())
|
||||
|
||||
opts = []
|
||||
for count in range(len(bufhce_sites)):
|
||||
for opt in itertools.combinations(bufhce_sites, count + 1):
|
||||
opts.append(opt)
|
||||
|
||||
for gclk in gclks:
|
||||
for tile_name, sites in random.choice(opts):
|
||||
for site in sorted(sites):
|
||||
print(
|
||||
"""
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
BUFHCE buf_{site} (
|
||||
.I({wire_name})
|
||||
);""".format(
|
||||
site=site,
|
||||
wire_name=gclk,
|
||||
))
|
||||
sites.remove(site)
|
||||
break
|
||||
|
||||
print("endmodule")
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -72,6 +72,8 @@ $(eval $(call fuzzer,028-fifo-config,005-tilegrid))
|
|||
$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
|
||||
$(eval $(call fuzzer,050-pip-seed,005-tilegrid))
|
||||
$(eval $(call fuzzer,051-pip-imuxlout-bypalts,050-pip-seed))
|
||||
$(eval $(call fuzzer,052-pip-clkin,050-pip-seed))
|
||||
|
|
|
|||
|
|
@ -78,6 +78,14 @@ case "$1" in
|
|||
clk_hrow_top_r)
|
||||
sed < "$2" > "$tmp1" -e 's/^CLK_HROW\./CLK_HROW_TOP_R./' ;;
|
||||
|
||||
clk_bufg_bot_r)
|
||||
sed < "$2" > "$tmp1" -e 's/^CLK_BUFG\./CLK_BUFG_BOT_R./' ;;
|
||||
clk_bufg_top_r)
|
||||
sed < "$2" > "$tmp1" -e 's/^CLK_BUFG\./CLK_BUFG_TOP_R./' ;;
|
||||
|
||||
clk_bufg_rebuf)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
liob33)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
|
|
|
|||
|
|
@ -131,3 +131,20 @@ proc write_pip_txtdata {filename} {
|
|||
}
|
||||
close $fp
|
||||
}
|
||||
|
||||
# Generic non-ROI'd generate.tcl template
|
||||
proc generate_top {} {
|
||||
create_project -force -part $::env(XRAY_PART) design design
|
||||
read_verilog top.v
|
||||
synth_design -top top
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
||||
|
||||
place_design
|
||||
route_design
|
||||
|
||||
write_checkpoint -force design.dcp
|
||||
write_bitstream -force design.bit
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue