mirror of https://github.com/openXC7/prjxray.git
Run make format.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
c2df5c97eb
commit
953d64a7b9
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@ -122,7 +122,6 @@ def main():
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elif tile in active_gclks[src]:
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segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
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segmk.compile()
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segmk.write()
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@ -164,12 +164,11 @@ class ClockSources(object):
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assert x == 0
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y = y % 16
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assert i_wire in [0, 1], i_wire
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casco_wire = '{tile_type}_CK_BUFG_CASCO{casco_idx}'.format(
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tile_type=tile_type.replace('BUFG', 'HROW'),
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casco_idx=(y*2+i_wire))
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tile_type=tile_type.replace('BUFG', 'HROW'),
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casco_idx=(y * 2 + i_wire))
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if casco_wire not in todos:
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return None
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@ -213,8 +212,6 @@ class ClockSources(object):
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return None
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def check_allowed(mmcm_pll_dir, cmt):
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""" Check whether the CMT specified is in the allowed direction.
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@ -235,6 +232,7 @@ def check_allowed(mmcm_pll_dir, cmt):
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else:
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assert False, mmcm_pll_dir
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def read_todo():
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dsts = {}
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@ -249,6 +247,7 @@ def read_todo():
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return dsts
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def need_int_connections(todos):
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for srcs in todos.values():
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for src in srcs:
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@ -257,6 +256,7 @@ def need_int_connections(todos):
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return False
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def bufhce_in_todo(todos, site):
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if 'BUFHCE' in site:
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# CLK_HROW_CK_MUX_OUT_R9 -> X1Y9
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@ -275,6 +275,7 @@ def bufhce_in_todo(todos, site):
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else:
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return True
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def main():
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"""
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BUFHCE's can be driven from:
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@ -366,7 +367,7 @@ module top();
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if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
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for clk in pll_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
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clock_sources.add_clock_source(clk, site_to_cmt[site], loc)
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print(
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"""
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@ -391,8 +392,10 @@ module top();
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))
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for loc, _, site in gen_sites('BUFR'):
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clock_sources.add_bufg_clock_source('O_{site}'.format(site=site), site_to_cmt[site], loc)
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print("""
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clock_sources.add_bufg_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site], loc)
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print(
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"""
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wire O_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR bufr_{site} (
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@ -405,7 +408,7 @@ module top();
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gclks = []
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for _, _, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[2])):
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key=lambda x: BUFGCTRL_XY_FUN(x[2])):
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wire_name = 'gclk_{}'.format(site)
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gclks.append(wire_name)
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@ -440,8 +443,8 @@ module top();
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ignore0net=luts.get_next_output_net(),
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ce1net=luts.get_next_output_net(),
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ce0net=luts.get_next_output_net(),
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), file=bufgs)
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),
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file=bufgs)
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any_bufhce = False
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for tile_name, sites in gen_bufhce_sites():
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@ -457,9 +460,8 @@ module top();
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BUFHCE buf_{site} (
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.I(I_{site})
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);
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""".format(
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site=site,
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), file=bufhs)
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""".format(site=site, ),
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file=bufhs)
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if random.random() > .05:
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wire_name = clock_sources.get_random_source(site_to_cmt[site])
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@ -467,12 +469,13 @@ module top();
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if wire_name is None:
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continue
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print("""
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print(
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"""
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assign I_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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), file=bufhs)
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site=site,
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wire_name=wire_name,
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),
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file=bufhs)
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if not any_bufhce:
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for tile_name, sites in gen_bufhce_sites():
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@ -491,7 +494,7 @@ module top();
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INIT_OUT=random.randint(0, 1),
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CE_TYPE=verilog.quote(
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random.choice(('SYNC', 'ASYNC'))),
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IS_CE_INVERTED = random.randint(0, 1),
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IS_CE_INVERTED=random.randint(0, 1),
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site=site,
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wire_name=gclks[0],
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))
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@ -507,24 +510,28 @@ module top();
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used_only = random.random() < .25
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for loc, tile_type, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[2])):
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key=lambda x: BUFGCTRL_XY_FUN(x[2])):
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if random.randint(0, 1):
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wire_name = clock_sources.get_bufg_source(loc, tile_type, site, todos, 1, used_only)
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wire_name = clock_sources.get_bufg_source(
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loc, tile_type, site, todos, 1, used_only)
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if wire_name is not None:
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print("""
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print(
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"""
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assign I1_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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))
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site=site,
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wire_name=wire_name,
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))
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if random.randint(0, 1):
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wire_name = clock_sources.get_bufg_source(loc, tile_type, site, todos, 0, used_only)
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wire_name = clock_sources.get_bufg_source(
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loc, tile_type, site, todos, 0, used_only)
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if wire_name is not None:
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print("""
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print(
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"""
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assign I0_{site} = {wire_name};""".format(
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site=site,
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wire_name=wire_name,
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))
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site=site,
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wire_name=wire_name,
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))
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print("endmodule")
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@ -33,7 +33,9 @@ def load_pipfile(pipfile, verbose=False):
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return todos, tile_type
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def maketodo(pipfile, dbfile, intre, exclude_re=None, not_endswith=None, verbose=False):
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def maketodo(
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pipfile, dbfile, intre, exclude_re=None, not_endswith=None,
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verbose=False):
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'''
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db files start with INT., but pipfile lines start with INT_L
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Normalize by removing before the first dot
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