roi_harness: basys3 small ROI. Simplified build dir

Signed-off-by: John McMaster <johndmcmaster@gmail.com>

minitests/roi_harness/.gitignore

@@ -11,3 +11,5 @@
 /*.bit
 /*.bin
 /*.frm
+
+build

minitests/roi_harness/Makefile

@@ -1,9 +1,12 @@
+BUILD_DIR=build
+
+# official demo configuration
 all:
-	bash runme.sh
+	SMALL=Y BUILD_DIR=$(BUILD_DIR) XRAY_PINCFG=BASYS3-SWBUT ./runme.sh
 
 clean:
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
-	rm -rf out_* *~
+	rm -rf $(BUILD_DIR) *~
 
 .PHONY: all clean
 

minitests/roi_harness/runme.sh

@@ -1,19 +1,47 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
-# 12x8 CLBs
+# This script requires an XC7A50T family part
+
+set -ex
+
+source ${XRAY_DIR}/utils/environment.sh
+
+export XRAY_PINCFG=${XRAY_PINCFG:-ARTY-A7-SWBUT}
+export BUILD_DIR=${BUILD_DIR:-build}
+
+# not part of the normal DB
+# to generate:
+cat >/dev/null <<EOF
+pushd ${XRAY_DIR}
+source minitests/roi_harness/basys3.sh
+pushd fuzzers/001-part-yaml
+make clean
+make
+make pushdb
+popd
+popd
+EOF
+stat ${XRAY_DIR}/database/artix7/${XRAY_PART}.yaml >/dev/null
+
+# 6x by 18y CLBs (108)
 if [ $SMALL = Y ] ; then
     echo "Design: small"
-    export DIN_N=2
-    export DOUT_N=2
-    export XRAY_ROI=SLICE_X12Y100:SLICE_X27Y111
-# 50x8 CLBs
+    export PITCH=1
+    export DIN_N=8
+    export DOUT_N=8
+    export XRAY_ROI=SLICE_X12Y100:SLICE_X17Y117
+# 16x by 50y CLBs (800)
 else
     echo "Design: large"
+    export PITCH=3
     export DIN_N=8
     export DOUT_N=8
     export XRAY_ROI=SLICE_X12Y100:SLICE_X27Y149
 fi
 
+mkdir -p $BUILD_DIR
+pushd $BUILD_DIR
+
 cat >defines.v <<EOF
 \`ifndef DIN_N
 \`define DIN_N $DIN_N
@@ -24,13 +52,9 @@ cat >defines.v <<EOF
 \`endif
 EOF
 
-
-set -ex
-rm -f out_last
-vivado -mode batch -source runme.tcl
+vivado -mode batch -source ../runme.tcl
 test -z "$(fgrep CRITICAL vivado.log)"
 
-pushd out_last
 ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
 ${XRAY_SEGPRINT} -zd design.bits >design.segp
 ${XRAY_DIR}/tools/segprint2fasm.py design.segp design.fasm

minitests/roi_harness/runme.tcl

@@ -2,12 +2,21 @@
 # Your ROI should at least have a SLICEL on the left
 
 # Number of package inputs going to ROI
-set DIN_N "$::env(DIN_N)"
+set DIN_N 8
+if { [info exists ::env(DIN_N) ] } {
+    set DIN_N "$::env(DIN_N)"
+}
 # Number of ROI outputs going to package
-set DOUT_N "$::env(DOUT_N)"
+set DOUT_N 8
+if { [info exists ::env(DOUT_N) ] } {
+    set DOUT_N "$::env(DOUT_N)"
+}
 # How many rows between pins
 # Reduces routing pressure
-set PITCH 3
+set PITCH 1
+if { [info exists ::env(PITCH) ] } {
+    set PITCH "$::env(PITCH)"
+}
 
 # X12 in the ROI, X10 just to the left
 # Start at bottom left of ROI and work up
@@ -25,7 +34,7 @@ set Y_BASE $XRAY_ROI_Y0
 # set Y_DIN_BASE 100
 set Y_CLK_BASE $Y_BASE
 # Clock lut in middle
-set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
+set Y_DIN_BASE [expr "$Y_CLK_BASE + $PITCH"]
 # Sequential
 # set Y_DOUT_BASE [expr "$Y_DIN_BASE + $DIN_N"]
 # At top. This relieves routing pressure by spreading things out
@@ -37,12 +46,11 @@ set pincfg ""
 if { [info exists ::env(XRAY_PINCFG) ] } {
     set pincfg "$::env(XRAY_PINCFG)"
 }
-set roiv "roi_base.v"
+set roiv "../roi_base.v"
 if { [info exists ::env(XRAY_ROIV) ] } {
     set roiv "$::env(XRAY_ROIV)"
 }
 set roiv_trim [string map {.v v} $roiv]
-set outdir "out_${part}_${pincfg}_${roiv_trim}"
 
 puts "Environment"
 puts "  XRAY_ROI: $::env(XRAY_ROI)"
@@ -50,15 +58,11 @@ puts "  X_BASE: $X_BASE"
 puts "  Y_DIN_BASE: $Y_DIN_BASE"
 puts "  Y_CLK_BASE: $Y_CLK_BASE"
 puts "  Y_DOUT_BASE: $Y_DOUT_BASE"
-puts "  outdir: $outdir"
 
-file mkdir $outdir
-file link -symbolic out_last $outdir
-
-source ../../utils/utils.tcl
+source ../../../utils/utils.tcl
 
 create_project -force -part $::env(XRAY_PART) design design
-read_verilog top.v
+read_verilog ../top.v
 read_verilog $roiv
 set fixed_xdc ""
 if { [info exists ::env(XRAY_FIXED_XDC) ] } {
@@ -203,7 +207,7 @@ if {$fixed_xdc eq ""} {
 
     set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
-    #write_checkpoint -force $outdir/synth.dcp
+    #write_checkpoint -force synth.dcp
 }
 
 
@@ -298,7 +302,7 @@ if {$fixed_xdc eq ""} {
 }
 
 place_design
-#write_checkpoint -force $outdir/placed.dcp
+#write_checkpoint -force placed.dcp
 
 # Version with more error checking for missing end node
 # Will do best effort in this case
@@ -357,7 +361,7 @@ proc node2wire {node} {
 }
 
 # XXX: maybe add IOB?
-set fp [open "$outdir/design.txt" w]
+set fp [open "design.txt" w]
 puts $fp "name node pin wire"
 # Manual routing
 if {$fixed_xdc eq ""} {
@@ -434,10 +438,10 @@ if {$fixed_xdc eq ""} {
     set_property IS_ROUTE_FIXED 1 [get_nets -hierarchical]
     #set_property IS_LOC_FIXED 1 [get_cells -hierarchical]
     #set_property IS_BEL_FIXED 1 [get_cells -hierarchical]
-    write_xdc -force $outdir/fixed.xdc
+    write_xdc -force fixed.xdc
 }
 
-write_checkpoint -force $outdir/design.dcp
+write_checkpoint -force design.dcp
 #set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
-write_bitstream -force $outdir/design.bit
+write_bitstream -force design.bit