mirror of https://github.com/openXC7/prjxray.git
litghost
GitHub
commit
8df6ed1131
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@ -26,7 +26,7 @@ def drives_for_iostandard(iostandard):
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drives = [4, 8, 12, 16, 24]
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elif iostandard == 'LVCMOS12':
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drives = [4, 8, 12]
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elif iostandard == 'SSTL135':
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elif iostandard in ['SSTL135', 'SSTL15']:
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return ['_FIXED']
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else:
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drives = [4, 8, 12, 16]
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@ -34,8 +34,10 @@ def drives_for_iostandard(iostandard):
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return drives
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STEPDOWN_IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'SSTL135']
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IBUF_LOW_PWR_SUPPORTED = ['SSTL135']
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STEPDOWN_IOSTANDARDS = [
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'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'SSTL135', 'SSTL15'
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]
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IBUF_LOW_PWR_SUPPORTED = ['SSTL135', 'SSTL15']
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def main():
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@ -185,6 +187,7 @@ def main():
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drive_opts.add(mk_drive_opt(opt, drive_opt))
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drive_opts.add(mk_drive_opt("SSTL135", None))
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drive_opts.add(mk_drive_opt("SSTL15", None))
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segmaker.add_site_group_zero(
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segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'),
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@ -66,7 +66,7 @@ def main():
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iostandard_lines = []
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with open(args.input_rdb) as f:
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for l in f:
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if ('.SSTL135' in l or '.LVCMOS' in l
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if ('.SSTL' in l or '.LVCMOS' in l
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or '.LVTTL' in l) and 'IOB_' in l:
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iostandard_lines.append(l)
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else:
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@ -56,10 +56,12 @@ def run():
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'LVCMOS33',
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'LVTTL',
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'SSTL135',
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'SSTL15',
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]
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diff_map = {
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"SSTL135": ["DIFF_SSTL135"],
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"SSTL15": ["DIFF_SSTL15"],
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}
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IN_TERM_ALLOWED = [
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@ -81,7 +83,7 @@ def run():
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drives = [4, 8, 12, 16, 24]
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elif iostandard in ['LVCMOS12']:
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drives = [4, 8, 12]
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elif iostandard == 'SSTL135':
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elif iostandard in ['SSTL135', 'SSTL15']:
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drives = None
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else:
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drives = [4, 8, 12, 16]
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@ -104,7 +106,7 @@ def run():
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params['iobanks'] = iobanks
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if iostandard in ['SSTL135']:
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if iostandard in ['SSTL135', 'SSTL15']:
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for iobank in iobanks:
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params['INTERNAL_VREF'][iobank] = random.choice(
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(
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@ -24,8 +24,8 @@ proc dump_iobs {file_name} {
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close $fp
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}
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create_project -force -in_memory -name dump_iobs -part $::env(VIVADO_PART)
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create_project -force -in_memory -name dump_iobs -part $::env(PART)
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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dump_iobs "iobs-$::env(VIVADO_PART).csv"
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dump_iobs "iobs-$::env(PART).csv"
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@ -1,5 +1,4 @@
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PART?=xc7a50tfgg484-1
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VIVADO_PART?=$(PART)
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PART?=${XRAY_PART}
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BIT2FASM_ARGS= --part "$(XRAY_DIR)/database/$(XRAY_DATABASE)/$(PART)" --verbose
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@ -33,20 +32,20 @@ clean:
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@rm -rf features.csv
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@rm -rf results.json
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@rm -rf unknown_bits.jl
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@rm -rf iobs-$(VIVADO_PART).csv
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@rm -rf iobs-$(PART).csv
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iobs-$(VIVADO_PART).csv: ../dump_iobs.tcl
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env VIVADO_PART=$(VIVADO_PART) $(XRAY_VIVADO) -mode batch -source ../dump_iobs.tcl -nojournal -log dump_iobs.log
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iobs-$(PART).csv: ../dump_iobs.tcl
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env PART=$(PART) $(XRAY_VIVADO) -mode batch -source ../dump_iobs.tcl -nojournal -log dump_iobs.log
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designs.ok: iobs-$(VIVADO_PART).csv generate.py
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env VIVADO_PART=$(VIVADO_PART) python3 ./generate.py
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designs.ok: iobs-$(PART).csv generate.py
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env PART=$(PART) python3 ./generate.py
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touch designs.ok
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designs: designs.ok
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%.bit: %.v designs.ok ../syn+par.tcl
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mkdir -p build-$(basename $@)
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cd build-$(basename $@) && env PROJECT_NAME=$(basename $@) VIVADO_PART=${VIVADO_PART} $(XRAY_VIVADO) -mode batch -source ../../syn+par.tcl -nojournal -log ../$@.log
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cd build-$(basename $@) && env PROJECT_NAME=$(basename $@) PART=${PART} $(XRAY_VIVADO) -mode batch -source ../../syn+par.tcl -nojournal -log ../$@.log
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rm -rf *.backup.log
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%.fasm: %.bit
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@ -26,7 +26,6 @@ def load_iob_sites(file_name):
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for site_data in data:
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iob_sites[site_data["clock_region"]].append(site_data)
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print(data)
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return iob_sites
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@ -40,8 +39,14 @@ IOBUF_NOT_ALLOWED = [
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DIFF_MAP = {
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'SSTL135': 'DIFF_SSTL135',
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'SSTL15': 'DIFF_SSTL15',
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}
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VREF_ALLOWED = [
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'SSTL135',
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'SSTL15',
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]
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def gen_iosettings():
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"""
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@ -56,10 +61,10 @@ def gen_iosettings():
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'LVCMOS33',
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'LVTTL',
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'SSTL135',
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'SSTL15',
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# Those are available but not currently fuzzed.
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# 'SSTL135_R',
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# 'SSTL15',
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# 'SSTL15_R',
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# 'SSTL18_I',
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# 'SSTL18_II',
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@ -111,7 +116,7 @@ def run():
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"""
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# Load IOB data
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iob_sites = load_iob_sites("iobs-{}.csv".format(os.getenv("VIVADO_PART")))
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iob_sites = load_iob_sites("iobs-{}.csv".format(os.getenv("PART")))
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# Generate IOB site to package pin map and *M site to *S site map.
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site_to_pkg_pin = {}
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@ -135,6 +140,8 @@ def run():
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design_index = 0
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while True:
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print("Design #{}".format(design_index))
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num_inp = 0
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num_out = 0
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num_ino = 0
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@ -143,6 +150,9 @@ def run():
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region_data = []
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for region in sorted(list(iob_sites.keys())):
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# Get IO bank. All sites from a clock region have the same one.
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bank = iob_sites[region][0]["bank"]
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# Get IO settings
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try:
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iosettings = next(iosettings_gen)
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@ -188,13 +198,14 @@ def run():
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region_data.append(
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{
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"region": region,
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"bank": bank,
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"iosettings": iosettings,
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"unused_sites": unused_sites,
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"input": used_sites[0:2],
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"output": used_sites[2:4],
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"inout": used_sites[4:5],
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})
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print(region, iosettings)
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print("", region, iosettings)
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# No more
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if len(region_data) == 0:
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@ -234,6 +245,9 @@ module top (
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if slew is not None:
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obuf_param_str += ", .SLEW(\"{}\")".format(slew)
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bank = data["bank"]
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vref = "0.75" # FIXME: Maybe loop over VREFs too ?
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keys = {
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"region": data["region"],
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"ibuf_0_loc": data["input"][0],
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@ -264,6 +278,11 @@ module top (
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out_idx += 2
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ino_idx += 1
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# Set VREF if necessary
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if iostandard in VREF_ALLOWED:
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tcl += "set_property INTERNAL_VREF {} [get_iobanks {}]\n".format(
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vref, bank)
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# Single ended
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if not is_diff:
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@ -1,4 +1,4 @@
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create_project -force -name $env(PROJECT_NAME) -part $env(VIVADO_PART)
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create_project -force -name $env(PROJECT_NAME) -part $env(PART)
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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@ -186,7 +186,7 @@ def run(
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# unclear how to know which IOSTANDARD to use.
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missing_features = []
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for line in fasm.parse_fasm_string("""
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{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY
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{tile}.{site}.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.IN_ONLY
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{tile}.{site}.LVCMOS25_LVCMOS33_LVTTL.IN
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{tile}.{site}.PULLTYPE.PULLUP
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""".format(
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