Fix bugs found during review.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/030-iob/top.py

@@ -65,6 +65,7 @@ def run():
 
     tile_params = []
     params = []
+    any_idelay = False
     for tile, site in gen_sites():
         p = {}
         p['tile'] = tile
@@ -81,6 +82,7 @@ def run():
             if not p['IDELAY_ONLY']:
                 p['owire'] = luts.get_next_input_net()
             else:
+                any_idelay = True
                 p['owire'] = 'idelay_{site}'.format(**p)
 
             p['DRIVE'] = None
@@ -127,10 +129,13 @@ def run():
 `define N_DIO {n_dio}
 
 module top(input wire [`N_DI-1:0] di, output wire [`N_DO-1:0] do, inout wire [`N_DIO-1:0] dio);
-        (* KEEP, DONT_TOUCH *)
-        IDELAYCTRL();
     '''.format(n_di=i_idx, n_do=o_idx, n_dio=io_idx))
 
+    if any_idelay:
+        print('''
+        (* KEEP, DONT_TOUCH *)
+        IDELAYCTRL();''')
+
     # Always output a LUT6 to make placer happy.
     print('''
         (* KEEP, DONT_TOUCH *)

fuzzers/035-iob-ilogic/top.py

@@ -129,10 +129,10 @@ def use_iserdese2(p, luts, connects):
         p['ODATA_WIDTH'] = random.choice(data_widths)
         p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
 
-        if p['ODATA_WIDTH'] > 4 or verilog.unquote(p['ODATA_RATE']) == 'SDR':
-            p['TRISTATE_WIDTH'] = 1
-        else:
+        if p['ODATA_WIDTH'] == 4 and verilog.unquote(p['ODATA_RATE']) == 'DDR':
             p['TRISTATE_WIDTH'] = 4
+        else:
+            p['TRISTATE_WIDTH'] = 1
 
         print(
             """