mirror of https://github.com/openXC7/prjxray.git
minitests: flatten hiearchy
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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