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prjxray
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Add bits for SDP 36-bit BRAM. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-22 23:06:48 -08:00
parent 8fde4e2b4c
commit 890f12b1d4
2 changed files with 49 additions and 14 deletions
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20
fuzzers/025-bram-config/generate.py
View File

@ -79,10 +79,17 @@ def rw_width_tags(segmk, ps, site):
9 1 1 0
18 0 0 1
'''
for param in ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A",
"WRITE_WIDTH_B"]:
params = ["READ_WIDTH_A", "READ_WIDTH_B", "WRITE_WIDTH_A", "WRITE_WIDTH_B"]
for param in params:
set_val = int(ps[param])
if set_val == 0:
set_val = 1
if set_val >= 36:
continue
def mk(x):
return '%s_%u' % (param, x)
@ -136,7 +143,14 @@ def run():
isinv_tags(segmk, ps, site, clk_inverts[site])
bus_tags(segmk, ps, site)
rw_width_tags(segmk, ps, site)
if ps['RAM_MODE'] == '"TDP"':
rw_width_tags(segmk, ps, site)
segmk.add_site_tag(
site, 'SDP_READ_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['READ_WIDTH_A']) == 36)
segmk.add_site_tag(
site, 'SDP_WRITE_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['WRITE_WIDTH_B']) == 36)
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)

43
fuzzers/025-bram-config/top.py
View File

@ -50,7 +50,28 @@ def place_bram18(site, loci):
# Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
# also 0 and 36 aren't real sizes
# Bias choice to 18 as its needed to solve certain bits quickly
widths = [1, 2, 4, 9, 18, 18, 18, 18]
widths = [1, 2, 4, 9, 18, 18, 36]
mode = '"TDP"'
read_width_a = random.choice(widths)
write_width_b = random.choice(widths)
if read_width_a >= 36 or write_width_b >= 36:
read_width_b = 0
write_width_a = 0
mode = '"SDP"'
doa_reg = vrandbit()
dob_reg = doa_reg
write_modes = ["WRITE_FIRST", "READ_FIRST"]
rstreg_priority_a = verilog.quote(random.choice(priorities))
rstreg_priority_b = rstreg_priority_a
else:
read_width_b = random.choice(widths)
write_width_a = random.choice(widths)
doa_reg = vrandbit()
dob_reg = vrandbit()
rstreg_priority_a = verilog.quote(random.choice(priorities))
rstreg_priority_b = verilog.quote(random.choice(priorities))
params = {
'LOC': verilog.quote(site),
'IS_CLKARDCLK_INVERTED': vrandbit(),
@ -61,22 +82,22 @@ def place_bram18(site, loci):
'IS_RSTRAMB_INVERTED': vrandbit(),
'IS_RSTREGARSTREG_INVERTED': vrandbit(),
'IS_RSTREGB_INVERTED': vrandbit(),
'RAM_MODE': '"TDP"',
'RAM_MODE': mode,
'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
"DOA_REG": vrandbit(),
"DOB_REG": vrandbit(),
"DOA_REG": doa_reg,
"DOB_REG": dob_reg,
"SRVAL_A": vrandbits(18),
"SRVAL_B": vrandbits(18),
"INIT_A": vrandbits(18),
"INIT_B": vrandbits(18),
"READ_WIDTH_A": random.choice(widths),
"READ_WIDTH_B": random.choice(widths),
"WRITE_WIDTH_A": random.choice(widths),
"WRITE_WIDTH_B": random.choice(widths),
"READ_WIDTH_A": read_width_a,
"READ_WIDTH_B": read_width_b,
"WRITE_WIDTH_A": write_width_a,
"WRITE_WIDTH_B": write_width_b,
"RDADDR_COLLISION_HWCONFIG": verilog.quote(random.choice(collisions)),
"RSTREG_PRIORITY_A": verilog.quote(random.choice(priorities)),
"RSTREG_PRIORITY_B": verilog.quote(random.choice(priorities)),
"RSTREG_PRIORITY_A": rstreg_priority_a,
"RSTREG_PRIORITY_B": rstreg_priority_b,
}
return ('my_RAMB18E1', ports, params)
@ -204,7 +225,7 @@ def main():
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEA(1'b0),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),