mirror of https://github.com/openXC7/prjxray.git
Fix new BRAM36 features.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
91d91357b5
commit
88fc1f1b40
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@ -7,14 +7,14 @@
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# SPDX-License-Identifier: ISC
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# read/write width is relatively slow to resolve
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# Even slower with multi bit masks...
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N ?= 10
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N ?= 20
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include ../fuzzer.mk
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database: build/segbits_bramx.db
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build/segbits_bramx.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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${XRAY_SEGMATCH} -c 1 -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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build/segbits_bramx.db: build/segbits_bramx.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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@ -0,0 +1,29 @@
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RAMB36 features
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===============
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This fuzzer emits features that only are used in the RAMB36E1 cell. There are
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3 categories:
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- ECC
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- RAM extension
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- Odd address modes
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Odd address modes
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-----------------
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Most RAMB36E1 address widths are expressed by configuring the underlying
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RAMB18E1 to handle half of the data. So `RAMB36.READ_WIDTH = 4` is
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expressed as `RAM18_Y0.READ_WIDTH = 2` and `RAM18_Y1.READ_WIDTH = 2`. However
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two address widths (1 and 9) are odd (e.g. not divisible by 2). In these
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cases, a RAMB36E1 specific feature is used. So `RAMB36.READ_WIDTH = 9` is
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expressed as:
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- `RAMB18_Y0.READ_WIDTH_4`
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- `RAMB18_Y1.READ_WIDTH_4`
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- `RAMB36.BRAM36_READ_WIDTH_1`
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and `RAMB36.READ_WIDTH = 1` is expressed as:
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- `RAMB18_Y0.READ_WIDTH_1`
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- `RAMB18_Y1.READ_WIDTH_1`
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- `RAMB36.BRAM36_READ_WIDTH_1`
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@ -36,13 +36,23 @@ def main():
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if tile_param['BRAM36_IN_USE']:
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write_ram_ext_tags(segmk, tile_param)
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segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1)
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
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segmk.add_site_tag(
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tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
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else:
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segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0)
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for ab in 'ab':
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for rw in 'rw':
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if rw == 'r':
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dir = 'READ'
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else:
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dir = 'WRITE'
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width = tile_param['bram36_{}{}_width'.format(rw, ab)]
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tag = 'BRAM36_{}_WIDTH_{}_1'.format(dir, ab.upper())
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if width == 1:
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segmk.add_site_tag(
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tile_param['site'], tag, tile_param['BRAM36_IN_USE'])
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segmk.compile()
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segmk.write()
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@ -47,6 +47,9 @@ RAM_EXTENSION_OPTS = [
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"UPPER",
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]
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BRAM36_WIDTHS = [1, 2]
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BRAM36_TO_18_WIDTHS = {1: 1, 2: 1}
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def main():
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db = Database(util.get_db_root(), util.get_part())
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@ -59,9 +62,27 @@ module top();
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params = []
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for tile_name, bram36_site_name, bram18_site_name, fifo18_site_name in gen_bram36(
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grid):
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bram36_ra_width = random.choice(BRAM36_WIDTHS)
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bram36_wa_width = random.choice(BRAM36_WIDTHS)
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bram36_rb_width = random.choice(BRAM36_WIDTHS)
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bram36_wb_width = random.choice(BRAM36_WIDTHS)
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bram18_ra_width = BRAM36_TO_18_WIDTHS[bram36_ra_width]
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bram18_wa_width = BRAM36_TO_18_WIDTHS[bram36_wa_width]
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bram18_rb_width = BRAM36_TO_18_WIDTHS[bram36_rb_width]
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bram18_wb_width = BRAM36_TO_18_WIDTHS[bram36_wb_width]
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if random.random() < .8:
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ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
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ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
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if bram36_ra_width == 1 and bram36_wa_width == 1:
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ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
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else:
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ram_extension_a = 'NONE'
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if bram36_rb_width == 1 and bram36_wb_width == 1:
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ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
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else:
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ram_extension_b = 'NONE'
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en_ecc_read = random.randint(0, 1)
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en_ecc_write = random.randint(0, 1)
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@ -69,10 +90,10 @@ module top();
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'''
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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RAMB36E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1),
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.READ_WIDTH_A({bram36_ra_width}),
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.WRITE_WIDTH_A({bram36_wa_width}),
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.READ_WIDTH_B({bram36_rb_width}),
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.WRITE_WIDTH_B({bram36_wb_width}),
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.RAM_EXTENSION_A({ram_extension_a}),
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.RAM_EXTENSION_B({ram_extension_b}),
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.EN_ECC_READ({en_ecc_read}),
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@ -106,6 +127,10 @@ module top();
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ram_extension_b=verilog.quote(ram_extension_b),
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en_ecc_read=en_ecc_read,
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en_ecc_write=en_ecc_write,
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bram36_ra_width=bram36_ra_width,
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bram36_wa_width=bram36_wa_width,
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bram36_rb_width=bram36_rb_width,
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bram36_wb_width=bram36_wb_width,
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))
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params.append(
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@ -117,16 +142,20 @@ module top();
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'RAM_EXTENSION_B': ram_extension_b,
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'EN_ECC_READ': en_ecc_read,
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'EN_ECC_WRITE': en_ecc_write,
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'bram36_ra_width': bram36_ra_width,
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'bram36_wa_width': bram36_wa_width,
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'bram36_rb_width': bram36_rb_width,
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'bram36_wb_width': bram36_wb_width,
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})
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else:
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{bram18}" *)
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RAMB18E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1)
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.READ_WIDTH_A({bram18_ra_width}),
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.WRITE_WIDTH_A({bram18_wa_width}),
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.READ_WIDTH_B({bram18_rb_width}),
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.WRITE_WIDTH_B({bram18_wb_width})
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) bram_{bram18} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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@ -153,10 +182,10 @@ module top();
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(* KEEP, DONT_TOUCH, LOC = "{fifo18}" *)
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RAMB18E1 #(
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.READ_WIDTH_A(1),
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.WRITE_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_B(1)
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.READ_WIDTH_A({bram18_ra_width}),
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.WRITE_WIDTH_A({bram18_wa_width}),
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.READ_WIDTH_B({bram18_rb_width}),
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.WRITE_WIDTH_B({bram18_wb_width})
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) bram_{fifo18} (
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.CLKARDCLK(),
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.CLKBWRCLK(),
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@ -183,6 +212,10 @@ module top();
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'''.format(
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bram18=bram18_site_name,
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fifo18=fifo18_site_name,
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bram18_ra_width=bram18_ra_width,
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bram18_wa_width=bram18_wa_width,
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bram18_rb_width=bram18_rb_width,
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bram18_wb_width=bram18_wb_width,
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))
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params.append(
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@ -190,6 +223,10 @@ module top();
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'tile': tile_name,
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'BRAM36_IN_USE': False,
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'site': bram36_site_name,
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'bram36_ra_width': bram36_ra_width,
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'bram36_wa_width': bram36_wa_width,
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'bram36_rb_width': bram36_rb_width,
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'bram36_wb_width': bram36_wb_width,
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})
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print("endmodule")
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