mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1576 from antmicro/add-pcie-int-interface-pips
062-pcie-int-pips: add DELAY PIPs fuzzer
This commit is contained in:
litghost
GitHub
commit
87c1af0d77
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@ -0,0 +1,60 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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export FUZDIR=$(shell pwd)
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PIP_TYPE?=pcie_int_interface
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SEG_TYPE?=pcie_int_interface
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PIPLIST_TCL=$(FUZDIR)/pcie_int_interface_pip_list.tcl
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BUILD_DIR = build
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RUN_OK = run.ok
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TODO_RE=".*"
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MAKETODO_FLAGS=--pip-type ${PIP_TYPE} --seg-type $(SEG_TYPE) --re $(TODO_RE) --sides "l,r"
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N = 5
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SEGMATCH_FLAGS=-c 1
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A_PIPLIST=pcie_int_interface_l.txt
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CHECK_ARGS= --zero-entries --min-iters 1 --max-iters 2
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include ../pip_loop.mk
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$(BUILD_DIR)/segbits_pcie_int_interface.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb \
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$(shell find $(BUILD_DIR) -name segdata_pcie_int_interface_l.txt)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb \
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$(shell find $(BUILD_DIR) -name segdata_pcie_int_interface_r.txt)
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RDBS = $(BUILD_DIR)/segbits_pcie_int_interface.rdb
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database: ${RDBS}
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_pcie_int_interface_l.db
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${XRAY_DBFIXUP} --db-root $(BUILD_DIR) --zero-db bits.dbf \
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--seg-fn-in $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb \
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--seg-fn-out $(BUILD_DIR)/segbits_pcie_int_interface_r.db
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# Keep a copy to track iter progress
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cp $(BUILD_DIR)/segbits_pcie_int_interface_l.rdb $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_l.rdb
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cp $(BUILD_DIR)/segbits_pcie_int_interface_l.db $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_l.db
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cp $(BUILD_DIR)/segbits_pcie_int_interface_r.rdb $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_r.rdb
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cp $(BUILD_DIR)/segbits_pcie_int_interface_r.db $(BUILD_DIR)/$(ITER)/segbits_pcie_int_interface_r.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db $(BUILD_DIR)/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} pcie_int_interface_l $(BUILD_DIR)/segbits_pcie_int_interface_l.db
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XRAY_DATABASE_DIR=$(BUILD_DIR)/database ${XRAY_MERGEDB} pcie_int_interface_r $(BUILD_DIR)/segbits_pcie_int_interface_r.db
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pushdb: database
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${XRAY_MERGEDB} pcie_int_interface_l $(BUILD_DIR)/segbits_pcie_int_interface_l.db
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${XRAY_MERGEDB} pcie_int_interface_r $(BUILD_DIR)/segbits_pcie_int_interface_r.db
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.PHONY: database pushdb run clean
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@ -0,0 +1,98 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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if frame not in [26, 27]:
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return False
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return True
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def read_pip_data(pipfile, pipdata, tile_ports):
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'pcie_int_interface', pipfile)) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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read_pip_data('pcie_int_interface_l.txt', pipdata, tile_ports)
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read_pip_data('pcie_int_interface_r.txt', pipdata, tile_ports)
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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if not tile.startswith('PCIE_INT_INTERFACE'):
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continue
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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else:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -0,0 +1,64 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc route_delay {} {
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set nets [get_nets]
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foreach net $nets {
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set wire [get_wires -of_objects $net -filter { TILE_NAME =~ "*PCIE_INT_INTERFACE*" && NAME =~ "*IMUX*OUT*" }]
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if { $wire == "" } {
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continue
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}
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if { rand() < 0.30 } {
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continue
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}
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set parts [split $wire "/"]
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set tile_name [lindex $parts 0]
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set wire_name [lindex $parts 1]
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set delay_wire_name [string map {OUT DELAY} $wire_name]
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set delay_node [get_nodes $tile_name/$delay_wire_name]
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if { $delay_node == "" } {
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exit 1
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}
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route_design -unroute -nets $net
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puts "Attempting to route net $net through $delay_node."
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route_via $net [list $delay_node]
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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route_design -directive Quick
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route_delay
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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@ -0,0 +1,48 @@
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# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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proc print_tile_pips {tile_type filename} {
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set fp [open $filename w]
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set pips [dict create]
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foreach tile [get_tiles -filter "TYPE =~ $tile_type*"] {
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foreach pip [lsort [get_pips -of_objects $tile]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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# Skip pips with disconnected nodes
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set src_node [get_nodes -of_objects $src]
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if { $src_node == {} } {
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continue
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}
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set dst_node [get_nodes -of_objects $dst]
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if { $dst_node == {} } {
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continue
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}
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set src_wire [regsub {.*/} $src ""]
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set src_delay_match [regexp {DELAY} $src_wire]
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if { $src_delay_match } {
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set pip_string "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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if ![dict exists $pips $pip_string] {
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puts $fp $pip_string
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dict set pips $pip_string 1
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}
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}
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}
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}
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close $fp
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}
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create_project -force -part $::env(XRAY_PART) design design
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set_property design_mode PinPlanning [current_fileset]
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open_io_design -name io_1
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print_tile_pips PCIE_INT_INTERFACE_L pcie_int_interface_l.txt
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print_tile_pips PCIE_INT_INTERFACE_R pcie_int_interface_r.txt
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@ -0,0 +1,179 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
|
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#
|
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# Use of this source code is governed by a ISC-style
|
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# license that can be found in the LICENSE file or at
|
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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ports = {
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"PCIE_2_1": [
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("CFGERRACSN", 1),
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("CFGERRATOMICEGRESSBLOCKEDN", 1),
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("CFGERRCORN", 1),
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("CFGERRCPLABORTN", 1),
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("CFGERRCPLTIMEOUTN", 1),
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("CFGERRCPLUNEXPECTN", 1),
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("CFGERRECRCN", 1),
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("CFGERRINTERNALCORN", 1),
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("CFGERRINTERNALUNCORN", 1),
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("CFGERRLOCKEDN", 1),
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("CFGERRMALFORMEDN", 1),
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("CFGERRMCBLOCKEDN", 1),
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("CFGERRNORECOVERYN", 1),
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("CFGERRPOISONEDN", 1),
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("CFGERRPOSTEDN", 1),
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("CFGERRURN", 1),
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("CFGFORCECOMMONCLOCKOFF", 1),
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("CFGFORCEEXTENDEDSYNCON", 1),
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("CFGINTERRUPTASSERTN", 1),
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("CFGINTERRUPTN", 1),
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("CFGINTERRUPTSTATN", 1),
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("CFGMGMTRDENN", 1),
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("CFGMGMTWRENN", 1),
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("CFGMGMTWRREADONLYN", 1),
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("CFGMGMTWRRW1CASRWN", 1),
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("CFGPMFORCESTATEENN", 1),
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("CFGPMHALTASPML0SN", 1),
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("CFGPMHALTASPML1N", 1),
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("CFGPMSENDPMETON", 1),
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("CFGPMTURNOFFOKN", 1),
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("CFGPMWAKEN", 1),
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("CFGTRNPENDINGN", 1),
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("CMRSTN", 1),
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("CMSTICKYRSTN", 1),
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("DBGSUBMODE", 1),
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("DLRSTN", 1),
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("DRPCLK", 1),
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("DRPEN", 1),
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("DRPWE", 1),
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("FUNCLVLRSTN", 1),
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("LL2SENDASREQL1", 1),
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("LL2SENDENTERL1", 1),
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("LL2SENDENTERL23", 1),
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("LL2SENDPMACK", 1),
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("LL2SUSPENDNOW", 1),
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("LL2TLPRCV", 1),
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("PIPECLK", 1),
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("PIPERX0CHANISALIGNED", 1),
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("PIPERX0ELECIDLE", 1),
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("PIPERX0PHYSTATUS", 1),
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("PIPERX0VALID", 1),
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("PIPERX1CHANISALIGNED", 1),
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("PIPERX1ELECIDLE", 1),
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("PIPERX1PHYSTATUS", 1),
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("PIPERX1VALID", 1),
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("PIPERX2CHANISALIGNED", 1),
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("PIPERX2ELECIDLE", 1),
|
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("PIPERX2PHYSTATUS", 1),
|
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("PIPERX2VALID", 1),
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("PIPERX3CHANISALIGNED", 1),
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("PIPERX3ELECIDLE", 1),
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("PIPERX3PHYSTATUS", 1),
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("PIPERX3VALID", 1),
|
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("PIPERX4CHANISALIGNED", 1),
|
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("PIPERX4ELECIDLE", 1),
|
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("PIPERX4PHYSTATUS", 1),
|
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("PIPERX4VALID", 1),
|
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("PIPERX5CHANISALIGNED", 1),
|
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("PIPERX5ELECIDLE", 1),
|
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("PIPERX5PHYSTATUS", 1),
|
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("PIPERX5VALID", 1),
|
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("PIPERX6CHANISALIGNED", 1),
|
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("PIPERX6ELECIDLE", 1),
|
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("PIPERX6PHYSTATUS", 1),
|
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("PIPERX6VALID", 1),
|
||||
("PIPERX7CHANISALIGNED", 1),
|
||||
("PIPERX7ELECIDLE", 1),
|
||||
("PIPERX7PHYSTATUS", 1),
|
||||
("PIPERX7VALID", 1),
|
||||
("PLDIRECTEDLINKAUTON", 1),
|
||||
("PLDIRECTEDLINKSPEED", 1),
|
||||
("PLDIRECTEDLTSSMNEWVLD", 1),
|
||||
("PLDIRECTEDLTSSMSTALL", 1),
|
||||
("PLDOWNSTREAMDEEMPHSOURCE", 1),
|
||||
("PLRSTN", 1),
|
||||
("PLTRANSMITHOTRST", 1),
|
||||
("PLUPSTREAMPREFERDEEMPH", 1),
|
||||
("SYSRSTN", 1),
|
||||
("TL2ASPMSUSPENDCREDITCHECK", 1),
|
||||
("TL2PPMSUSPENDREQ", 1),
|
||||
("TLRSTN", 1),
|
||||
("TRNRDSTRDY", 1),
|
||||
("TRNRFCPRET", 1),
|
||||
("TRNRNPOK", 1),
|
||||
("TRNRNPREQ", 1),
|
||||
("TRNTCFGGNT", 1),
|
||||
("TRNTDLLPSRCRDY", 1),
|
||||
("TRNTECRCGEN", 1),
|
||||
("TRNTEOF", 1),
|
||||
("TRNTERRFWD", 1),
|
||||
("TRNTSOF", 1),
|
||||
("TRNTSRCDSC", 1),
|
||||
("TRNTSRCRDY", 1),
|
||||
("TRNTSTR", 1),
|
||||
("USERCLK2", 1),
|
||||
("USERCLK", 1),
|
||||
("CFGERRAERHEADERLOG", 128),
|
||||
("TRNTD", 128),
|
||||
("CFGDEVID", 16),
|
||||
("CFGSUBSYSID", 16),
|
||||
("CFGSUBSYSVENDID", 16),
|
||||
("CFGVENDID", 16),
|
||||
("DRPDI", 16),
|
||||
("PIPERX0DATA", 16),
|
||||
("PIPERX1DATA", 16),
|
||||
("PIPERX2DATA", 16),
|
||||
("PIPERX3DATA", 16),
|
||||
("PIPERX4DATA", 16),
|
||||
("PIPERX5DATA", 16),
|
||||
("PIPERX6DATA", 16),
|
||||
("PIPERX7DATA", 16),
|
||||
("CFGPMFORCESTATE", 2),
|
||||
("DBGMODE", 2),
|
||||
("PIPERX0CHARISK", 2),
|
||||
("PIPERX1CHARISK", 2),
|
||||
("PIPERX2CHARISK", 2),
|
||||
("PIPERX3CHARISK", 2),
|
||||
("PIPERX4CHARISK", 2),
|
||||
("PIPERX5CHARISK", 2),
|
||||
("PIPERX6CHARISK", 2),
|
||||
("PIPERX7CHARISK", 2),
|
||||
("PLDIRECTEDLINKCHANGE", 2),
|
||||
("PLDIRECTEDLINKWIDTH", 2),
|
||||
("TRNTREM", 2),
|
||||
("CFGDSFUNCTIONNUMBER", 3),
|
||||
("CFGFORCEMPS", 3),
|
||||
("PIPERX0STATUS", 3),
|
||||
("PIPERX1STATUS", 3),
|
||||
("PIPERX2STATUS", 3),
|
||||
("PIPERX3STATUS", 3),
|
||||
("PIPERX4STATUS", 3),
|
||||
("PIPERX5STATUS", 3),
|
||||
("PIPERX6STATUS", 3),
|
||||
("PIPERX7STATUS", 3),
|
||||
("PLDBGMODE", 3),
|
||||
("TRNFCSEL", 3),
|
||||
("CFGMGMTDI", 32),
|
||||
("TRNTDLLPDATA", 32),
|
||||
("CFGMGMTBYTEENN", 4),
|
||||
("CFGERRTLPCPLHEADER", 48),
|
||||
("CFGAERINTERRUPTMSGNUM", 5),
|
||||
("CFGDSDEVICENUMBER", 5),
|
||||
("CFGPCIECAPINTERRUPTMSGNUM", 5),
|
||||
("PL2DIRECTEDLSTATE", 5),
|
||||
("PLDIRECTEDLTSSMNEW", 6),
|
||||
("CFGDSN", 64),
|
||||
("MIMRXRDATA", 68),
|
||||
("MIMTXRDATA", 69),
|
||||
("CFGDSBUSNUMBER", 8),
|
||||
("CFGINTERRUPTDI", 8),
|
||||
("CFGPORTNUMBER", 8),
|
||||
("CFGREVID", 8),
|
||||
("DRPADDR", 9),
|
||||
("CFGMGMTDWADDR", 10),
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2017-2020 The Project X-Ray Authors.
|
||||
#
|
||||
# Use of this source code is governed by a ISC-style
|
||||
# license that can be found in the LICENSE file or at
|
||||
# https://opensource.org/licenses/ISC
|
||||
#
|
||||
# SPDX-License-Identifier: ISC
|
||||
import os
|
||||
import random
|
||||
import math
|
||||
random.seed(int(os.getenv("SEED"), 16))
|
||||
from prjxray import util
|
||||
from prjxray.lut_maker import LutMaker
|
||||
from prjxray.db import Database
|
||||
|
||||
from ports import ports
|
||||
|
||||
|
||||
def print_site(ports, luts, site, site_type):
|
||||
verilog_ports = ""
|
||||
verilog_wires = ""
|
||||
|
||||
for port, width in ports:
|
||||
verilog_ports += """
|
||||
.{port}({port}_{site}),""".format(
|
||||
port=port, site=site)
|
||||
verilog_wires += "wire [{}:0] {}_{};\n".format(width - 1, port, site)
|
||||
|
||||
for idx in range(0, width):
|
||||
verilog_wires += "assign {}_{}[{}] = {};\n".format(
|
||||
port, site, idx, luts.get_next_output_net())
|
||||
|
||||
verilog_wires += "\n"
|
||||
|
||||
verilog_ports = verilog_ports.rstrip(",")
|
||||
|
||||
print(
|
||||
"""
|
||||
{wires}
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
{site_type} {site}_instance (
|
||||
{ports}
|
||||
);""".format(
|
||||
wires=verilog_wires,
|
||||
ports=verilog_ports,
|
||||
site=site,
|
||||
site_type=site_type))
|
||||
|
||||
|
||||
def main():
|
||||
db = Database(util.get_db_root(), util.get_part())
|
||||
grid = db.grid()
|
||||
|
||||
luts = LutMaker()
|
||||
|
||||
def gen_sites(desired_site_type):
|
||||
for tile_name in sorted(grid.tiles()):
|
||||
loc = grid.loc_of_tilename(tile_name)
|
||||
gridinfo = grid.gridinfo_at_loc(loc)
|
||||
for site, site_type in gridinfo.sites.items():
|
||||
if site_type == desired_site_type:
|
||||
yield tile_name, site
|
||||
|
||||
print('''
|
||||
module top();
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy();
|
||||
''')
|
||||
|
||||
for site_type in ["PCIE_2_1"]:
|
||||
for _, site in gen_sites(site_type):
|
||||
print_site(ports[site_type], luts, site, site_type)
|
||||
|
||||
for l in luts.create_wires_and_luts():
|
||||
print(l)
|
||||
|
||||
print('endmodule')
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -158,6 +158,7 @@ $(eval $(call fuzzer,076-ps7,,all))
|
|||
endif
|
||||
ifeq ($(XRAY_DATABASE),artix7)
|
||||
$(eval $(call fuzzer,061-pcie-conf,005-tilegrid,all))
|
||||
$(eval $(call fuzzer,062-pcie-int-pips,005-tilegrid,all))
|
||||
$(eval $(call fuzzer,063-gtp-common-conf,005-tilegrid,part))
|
||||
$(eval $(call fuzzer,064-gtp-channel-conf,005-tilegrid,part))
|
||||
$(eval $(call fuzzer,065-gtp-common-pips,005-tilegrid,part))
|
||||
|
|
|
|||
|
|
@ -160,6 +160,12 @@ case "$1" in
|
|||
pcie_bot)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
pcie_int_interface_l)
|
||||
sed < "$2" > "$tmp1" -e 's/^PCIE_INT_INTERFACE\./PCIE_INT_INTERFACE_L./' ;;
|
||||
|
||||
pcie_int_interface_r)
|
||||
sed < "$2" > "$tmp1" -e 's/^PCIE_INT_INTERFACE\./PCIE_INT_INTERFACE_R./' ;;
|
||||
|
||||
gtp_common)
|
||||
cp "$2" "$tmp1" ;;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue