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prjxray
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Initial import 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf 2017-07-20 09:57:10 +02:00
commit 858f50d9bb
5 changed files with 105 additions and 0 deletions
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8
gridinfo/.gitignore vendored Normal file
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/.Xil
/design
/design.v
/design.xdc
/design.tcl
/design.log
/design.dcp
/logicframes_SLICE_*.bit

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set sites [get_sites -filter {(SITE_TYPE == "SLICEL" || SITE_TYPE == "SLICEM") && (NAME =~ "*Y0" || NAME =~ "*Y50" || NAME =~ "*Y?00" || NAME =~ "*Y?50")}]
foreach site $sites {
puts ""; puts ""; puts ""; puts ""; puts ""; puts ""
puts "=========================== $site ==========================="
set_property LOC $site [get_cells lut]
route_design
set_property INIT 64'h8000000000000000 [get_cells lut]
write_bitstream -force logicframes_${site}_0.bit
set_property INIT 64'h8000000000000001 [get_cells lut]
write_bitstream -force logicframes_${site}_1.bit
}

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#!/bin/bash
set -ex
source ../settings.sh
cat > design.xdc << EOT
set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports I[0]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports I[1]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports I[2]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports I[3]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_04 IOSTANDARD LVCMOS33} [get_ports I[4]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_05 IOSTANDARD LVCMOS33} [get_ports I[5]]
set_property -dict {PACKAGE_PIN $XRAY_PIN_06 IOSTANDARD LVCMOS33} [get_ports O]
set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} [get_cells lut]
set_property -dict {IS_LOC_FIXED 1 IS_BEL_FIXED 1 BEL SLICEL.A6LUT} [get_cells lut]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
EOT
cat > design.v << EOT
module top(input [5:0] I, output O);
LUT6 #(.INIT(64'h8000000000000000)) lut (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.I4(I[4]),
.I5(I[5]),
.O(O)
);
endmodule
EOT
cat > design.tcl << EOT
create_project -force -part $XRAY_PART design design
read_xdc design.xdc
read_verilog design.v
synth_design -top top
place_design
route_design
write_checkpoint -force design.dcp
source logicframes.tcl
source tiledata.tcl
EOT
rm -f design.log
vivado -nojournal -log design.log -mode batch -source design.tcl

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foreach tile [get_tiles] {
foreach prop [list_property $tile] {
puts "--tiledata-- TILEPROP $tile $prop [get_property $prop $tile]"
}
foreach site [get_sites -quiet -of_objects $tile] {
puts "--tiledata-- TILESITE $tile $site"
}
}
foreach site [get_sites] {
foreach prop [list_property $site] {
puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]"
}
}

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export XRAY_PART="xc7a50tfgg484-1"
export XRAY_PIN_00="E22"
export XRAY_PIN_01="D22"
export XRAY_PIN_02="E21"
export XRAY_PIN_03="D21"
export XRAY_PIN_04="G21"
export XRAY_PIN_05="G22"
export XRAY_PIN_06="F21"