mirror of https://github.com/openXC7/prjxray.git
timfuz: remove nodes from timing4.txt
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
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0a7c68b5a0
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85862394ce
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@ -38,8 +38,8 @@ proc list_format {l delim} {
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return $ret
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}
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proc line_net_external {fp net src_site src_site_type src_site_pin src_bel src_bel_pin dst_site dst_site_type dst_site_pin dst_bel dst_bel_pin ico fast_max fast_min slow_max slow_min pips_out nodes_out wires_out} {
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$nodes_out,$wires_out"
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proc line_net_external {fp net src_site src_site_type src_site_pin src_bel src_bel_pin dst_site dst_site_type dst_site_pin dst_bel dst_bel_pin ico fast_max fast_min slow_max slow_min pips_out wires_out} {
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$wires_out"
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}
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proc line_net_internal {fp net site site_type src_bel src_bel_pin dst_bel dst_bel_pin ico fast_max fast_min slow_max slow_min} {
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@ -52,17 +52,16 @@ proc line_net_internal {fp net site site_type src_bel src_bel_pin dst_bel dst_be
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set dst_site_pin ""
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set pips_out ""
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set nodes_out ""
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set wires_out ""
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$nodes_out,$wires_out"
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puts $fp "NET,$net,$src_site,$src_site_type,$src_site_pin,$src_bel,$src_bel_pin,$dst_site,$dst_site_type,$dst_site_pin,$dst_bel,$dst_bel_pin,$ico,$fast_max,$fast_min,$slow_max,$slow_min,$pips_out,$wires_out"
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}
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proc write_info4 {} {
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set outdir "."
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set fp [open "$outdir/timing4.txt" w]
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# bel as site/bel, so don't bother with site
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puts $fp "linetype,net,src_site,src_site_type,src_site_pin,src_bel,src_bel_pin,dst_site,dst_site_type,dst_site_pin,dst_bel,dst_bel_pin,ico,fast_max,fast_min,slow_max,slow_min,pips,inodes,wires"
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puts $fp "linetype,net,src_site,src_site_type,src_site_pin,src_bel,src_bel_pin,dst_site,dst_site_type,dst_site_pin,dst_bel,dst_bel_pin,ico,fast_max,fast_min,slow_max,slow_min,pips,wires"
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set TIME_start [clock clicks -milliseconds]
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set equations 0
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@ -184,19 +183,11 @@ proc write_info4 {} {
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}
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set pips_out [list_format "$pips_out" "|"]
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# Write nodes
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# XXX: remove? don't think I care about these
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# most for debugging at this point
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set nodes [get_nodes -of_objects $net -from $src_site_pin -to $dst_site_pin]
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if {$nodes eq ""} {
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puts "ERROR: no nodes"
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return
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}
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foreach node $nodes {
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set nwires [llength [get_wires -of_objects $node]]
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lappend nodes_out "$node:$nwires"
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}
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set nodes_out [list_format "$nodes_out" "|"]
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set wires [get_wires -of_objects $nodes]
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# Write wires
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@ -207,7 +198,7 @@ proc write_info4 {} {
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set wires_out [list_format "$wires_out" "|"]
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incr lines_some_int
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line_net_external $fp $net $src_site $src_site_type $src_site_pin $src_bel $src_bel_pin $dst_site $dst_site_type $dst_site_pin $dst_bel $dst_bel_pin $ico $fast_max $fast_min $slow_max $slow_min $pips_out $nodes_out $wires_out
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line_net_external $fp $net $src_site $src_site_type $src_site_pin $src_bel $src_bel_pin $dst_site $dst_site_type $dst_site_pin $dst_bel $dst_bel_pin $ico $fast_max $fast_min $slow_max $slow_min $pips_out $wires_out
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}
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}
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}
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@ -29,17 +29,6 @@ def parse_pips(pips, speed_i2s):
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return [parse_pip(pip, speed_i2s) for pip in pips.split('|')]
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def parse_node(s):
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node, nwires = s.split(':')
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return node, int(nwires)
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def parse_nodes(nodes):
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if not nodes:
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return []
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return [parse_node(node) for node in nodes.split('|')]
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def parse_wire(s, speed_i2s):
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# CLBLM_R_X3Y80/CLBLM_M_D6:952
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wirestr, speed_index = s.split(':')
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@ -55,7 +44,7 @@ def parse_wires(wires, speed_i2s):
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def gen_timing4(fn, speed_i2s):
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f = open(fn, 'r')
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header_want = "linetype,net,src_site,src_site_type,src_site_pin,src_bel,src_bel_pin,dst_site,dst_site_type,dst_site_pin,dst_bel,dst_bel_pin,ico,fast_max,fast_min,slow_max,slow_min,pips,inodes,wires"
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header_want = "linetype,net,src_site,src_site_type,src_site_pin,src_bel,src_bel_pin,dst_site,dst_site_type,dst_site_pin,dst_bel,dst_bel_pin,ico,fast_max,fast_min,slow_max,slow_min,pips,wires"
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ncols = len(header_want.split(','))
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# src_bel dst_bel ico fast_max fast_min slow_max slow_min pips
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@ -78,7 +67,7 @@ def gen_timing4(fn, speed_i2s):
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def net_line():
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assert len(parts) == ncols, "Expected %u parts, got %u" % (
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ncols, len(parts))
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_lintype, net, src_site, src_site_type, src_site_pin, src_bel, src_bel_pin, dst_site, dst_site_type, dst_site_pin, dst_bel, dst_bel_pin, ico, fast_max, fast_min, slow_max, slow_min, pips, nodes, wires = parts
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_lintype, net, src_site, src_site_type, src_site_pin, src_bel, src_bel_pin, dst_site, dst_site_type, dst_site_pin, dst_bel, dst_bel_pin, ico, fast_max, fast_min, slow_max, slow_min, pips, wires = parts
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return {
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'net': net,
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'src': {
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@ -104,7 +93,6 @@ def gen_timing4(fn, speed_i2s):
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},
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'ico': int(ico),
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'pips': parse_pips(pips, speed_i2s),
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'nodes': parse_nodes(nodes),
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'wires': parse_wires(wires, speed_i2s),
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'line': l,
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}
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