mirror of https://github.com/openXC7/prjxray.git
tilegrid: add comments
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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@ -213,7 +213,7 @@ def make_segments(database, tiles_by_grid, tile_baseaddrs, verbose=False):
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'''
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BRAM/DSP itself is at the base y address
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There is one huge switchbox on the right for the 5 tiles
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These fan into 5 BRAM_INT_INTERFACE tiles each which feed into their own CENTER_INTER (just like a CLB has)
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These fan into 5 BRAM_INT_INTERFACE tiles each which feed into their own CENTER_INTER (just like a CLB has)
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'''
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if k == 0:
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tiles = [tile_name, interface_tile_name, int_tile_name]
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@ -270,7 +270,7 @@ def seg_base_addr_lr_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: L/R along INT column'''
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'''
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Create BRAM base addresses based on nearby CLBs
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ie if we have a BRAM_L, compute as nearby CLB_R base address + offset
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ie if we have a BRAM_L, compute as nearby CLB_R base address + offset
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'''
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verbose and print('')
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@ -336,18 +336,14 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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'''Populate segment base addresses: Up along INT/HCLK columns'''
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verbose and print('')
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'''
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All baseaddrs so far have 50 tiles above them to be derived
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However, once we start deriving, this is no longer true
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Copy the initial list so that any baseaddr encountered can safely be swept up
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'''
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# Copy the initial list containing only base addresses
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# and soon to have derived addresses
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src_segment_names = list()
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for segment_name in segments.keys():
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if "baseaddr" in segments[segment_name]:
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src_segment_names.append(segment_name)
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verbose and print('up_INT: %u base addresses' % len(src_segment_names))
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#verbose and print('\n'.join(sorted(src_segment_names)))
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for src_segment_name in sorted(src_segment_names):
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src_segment = segments[src_segment_name]
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@ -390,6 +386,24 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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'''
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Lookup BRAM0 tile associated with this segment
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Use it to locate in the grid, and find other BRAM0 related by tile offset
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From minitest:
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build/roi_bramd_bit01.diff (lowest BRAM coordinate)
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> bit_00c00000_000_00
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build/roi_bramds_bit01.diff
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> bit_00c00000_000_00
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> bit_00c00000_010_00
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> bit_00c00000_020_00
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> bit_00c00000_030_00
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> bit_00c00000_040_00
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> bit_00c00000_051_00
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> bit_00c00000_061_00
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> bit_00c00000_071_00
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> bit_00c00000_081_00
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> bit_00c00000_091_00
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'''
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src_tile_name = get_bramtile(database, src_segment)
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verbose and print(
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@ -400,18 +414,15 @@ def seg_base_addr_up_INT(database, segments, tiles_by_grid, verbose=False):
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for i in range(9):
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grid_y -= 5
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wordbase += 0x10
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# Skip HCLK
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if i == 4:
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grid_y -= 1
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wordbase += 1
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dst_tile = database[tiles_by_grid[(grid_x, grid_y)]]
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assert nolr(dst_tile['type']) == 'BRAM', dst_tile
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# FIXME: get actual numbers
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if i == 4:
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wordbase += 1
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else:
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wordbase += 2
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dst_segment_name = dst_tile["segment"]
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assert 'BRAM0' in dst_segment_name
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segments[dst_segment_name].setdefault(
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@ -438,10 +449,14 @@ def add_tile_bits(tile_db, baseaddr, offset, height):
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assert block_type not in bits
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block = bits.setdefault(block_type, {})
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# FDRI base address
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block["baseaddr"] = '0x%08X' % baseaddr
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# FDRI offset from baseaddr
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block["offset"] = offset
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# Number of words consumed (was: "words")
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block["height"] = height
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# Number of frames this entry is sretched across
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#block["frames"] = frames
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def add_bits(database, segments):
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'''Transfer segment data into tiles'''
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@ -452,14 +467,14 @@ def add_bits(database, segments):
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for tile_name in segments[segment_name]["tiles"]:
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tile_type = database[tile_name]["type"]
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height = {
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"CLBLL": 2,
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"CLBLM": 2,
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"INT": 2,
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"HCLK": 1,
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"BRAM": 10,
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"DSP": 10,
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"INT_INTERFACE": 0,
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"BRAM_INT_INTERFACE": 0,
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"CLBLL": 2,
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"CLBLM": 2,
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"INT": 2,
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"HCLK": 1,
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"BRAM": 10,
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"DSP": 10,
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"INT_INTERFACE": 0,
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"BRAM_INT_INTERFACE": 0,
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}.get(nolr(tile_type), None)
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if height is None:
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raise ValueError("Unknown tile type %s" % tile_type)
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