mirror of https://github.com/openXC7/prjxray.git
utils: sp6_bitstream_analyzer: Convert f-string to str.format()
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
d59247d9c6
commit
8054f88d40
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@ -144,8 +144,8 @@ class Bitstream:
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if verbose:
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print(
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"\tWord: ", hex(word),
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f'Type: {type}, Op: {opcodes[opcode]}, Addr: {reg_addr}, Words: {words}'
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)
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'Type: {}, Op: {}, Addr: {}, Words: {}'.format(
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type, opcodes[opcode], reg_addr, words))
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if opcode and reg_addr in conf_regs:
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payload_len = words
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continue
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@ -258,19 +258,19 @@ class Bitstream:
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if reg == "CMD":
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command = self.parse_command(word)
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if verbose:
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print(f"Command: {command}\n")
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print("Command: {}\n".format(command))
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elif reg == "FLR":
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frame_length = word
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if verbose:
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print(f"Frame length: {frame_length}\n")
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print("Frame length: {}\n".format(frame_length))
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elif reg == "COR1":
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conf_options = self.parse_cor1(word)
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if verbose:
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print(f"COR1 options: {conf_options}\n")
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print("COR1 options: {}\n".format(conf_options))
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elif reg == "COR2":
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conf_options = self.parse_cor2(word)
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if verbose:
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print(f"COR2 options: {conf_options}\n")
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print("COR2 options: {}\n".format(conf_options))
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elif reg == "IDCODE":
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assert payload_len < 3
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if payload_len == 2:
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@ -282,67 +282,69 @@ class Bitstream:
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elif reg == "MASK":
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mask = word
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if verbose:
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print(f"Mask value: {mask}\n")
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print("Mask value: {}\n".format(mask))
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elif reg == "CTL":
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ctl_options = self.parse_ctl(word)
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if verbose:
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print(f"CTL options: {ctl_options}\n")
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print("CTL options: {}\n".format(ctl_options))
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elif reg == "CCLK_FREQ":
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cclk_freq_options = self.parse_cclk_freq(word)
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if verbose:
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print(f"CCLK_FREQ options: {cclk_freq_options}\n")
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print("CCLK_FREQ options: {}\n".format(cclk_freq_options))
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elif reg == "PWRDN_REG":
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suspend_reg_options = self.parse_pwrdn(word)
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if verbose:
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print(f"{reg} options: {suspend_reg_options}\n")
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print("{} options: {}\n".format(reg, suspend_reg_options))
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elif reg == "EYE_MASK":
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eye_mask = self.parse_eye_mask(word)
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if verbose:
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print(f"{reg} options: {eye_mask}\n")
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print("{} options: {}\n".format(reg, eye_mask))
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elif reg == "HC_OPT_REG":
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hc_options = self.parse_hc_opt(word)
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if verbose:
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print(f"{reg} options: {hc_options}\n")
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print("{} options: {}\n".format(reg, hc_options))
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elif reg == "CWDT":
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cwdt_options = self.parse_cwdt(word)
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if verbose:
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print(f"{reg} options: {cwdt_options}\n")
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print("{} options: {}\n".format(reg, cwdt_options))
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elif reg == "PU_GWE":
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pu_gwe_sequence = self.parse_pu_gwe(word)
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if verbose:
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print(f"{reg} options: {pu_gwe_sequence}\n")
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print("{} options: {}\n".format(reg, pu_gwe_sequence))
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elif reg == "PU_GTS":
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pu_gts_sequence = self.parse_pu_gts(word)
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if verbose:
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print(f"{reg} options: {pu_gts_sequence}\n")
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print("{} options: {}\n".format(reg, pu_gts_sequence))
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elif reg == "MODE_REG":
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mode_options = self.parse_mode(word)
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if verbose:
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print(f"{reg} options: {mode_options}\n")
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print("{} options: {}\n".format(reg, mode_options))
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elif reg == "GENERAL1" or reg == "GENERAL2" \
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or reg == "GENERAL3" or reg == "GENERAL4" \
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or reg == "GENERAL5":
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general_options = word
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if verbose:
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print(f"{reg} options: {general_options}\n")
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print("{} options: {}\n".format(reg, general_options))
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elif reg == "SEU_OPT":
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seu_options = self.parse_seu(word)
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if verbose:
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print(f"{reg} options: {seu_options}\n")
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print("{} options: {}\n".format(reg, seu_options))
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elif reg == "EXP_SIGN":
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if payload_len == 2:
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self.exp_sign = word << 16
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elif payload_len == 1:
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self.exp_sign |= word
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if verbose:
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print(f"{reg}: {self.exp_sign}\n")
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print("{}: {}\n".format(reg, self.exp_sign))
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elif reg == "FAR_MAJ":
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if payload_len == 2:
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self.current_far_maj = word
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elif payload_len == 1:
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self.current_far_min = word
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if verbose:
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print(f"{reg}: {self.far_maj} FAR_MIN: {self.far_min}\n")
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print(
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"{}: {} FAR_MIN: {}\n".format(
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reg, self.far_maj, self.far_min))
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elif reg == "FDRI":
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if self.fdri_in_progress:
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self.frame_data.append(word)
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@ -357,7 +359,7 @@ class Bitstream:
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# Check if 0 words actually means read something
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payload_len = self.curr_fdri_write_len + 2
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if verbose:
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print(f"{reg}: {self.curr_fdri_write_len}\n")
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print("{}: {}\n".format(reg, self.curr_fdri_write_len))
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return payload_len
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elif reg == "CRC":
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if payload_len == 2:
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@ -365,7 +367,7 @@ class Bitstream:
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elif payload_len == 1:
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self.curr_crc_check |= word
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if verbose:
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print(f"{reg}: {self.curr_crc_check}\n")
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print("{}: {}\n".format(reg, self.curr_crc_check))
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payload_len -= 1
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return payload_len
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