Merge pull request #217 from mcmasterg/tilegrid_bram

BRAM pushdb

fuzzers/025-bram-config/Makefile

@@ -4,11 +4,11 @@ SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N)))
 SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
 
 database: $(SPECIMENS_OK)
-	${XRAY_SEGMATCH} -o build/seg_bramx.block_ram.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+	${XRAY_SEGMATCH} -o build/seg_bramx.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
 
 pushdb:
-	${XRAY_MERGEDB} bram_l.block_ram build/seg_bramx.block_ram.segbits
+	${XRAY_MERGEDB} bram_l build/seg_bramx.segbits
-	${XRAY_MERGEDB} bram_r.block_ram build/seg_bramx.block_ram.segbits
+	${XRAY_MERGEDB} bram_r build/seg_bramx.segbits
 
 build:
 	mkdir build

fuzzers/025-bram-config/generate.py

@@ -86,7 +86,7 @@ def write_mode_tags(segmk, ps, site):
 
 def run():
 
-    segmk = Segmaker("design.bits", verbose=True)
+    segmk = Segmaker("design.bits")
     #segmk.set_def_bt('BLOCK_RAM')
 
     print("Loading tags")

fuzzers/025-bram-config/top.py

@@ -32,15 +32,7 @@ def gen_brams():
     '''
     Correctly assign a site to either bram36 or 2x bram18
     '''
-    # FIXME
+    # XXX: mix 18 and 36?
-    #yield ('RAMBFIFO36E1', "RAMB36_X0Y20")
-    #return
-
-    #for _tile_name, site_name, _site_type in util.get_roi().gen_tiles():
-
-    #for site in gen_bram36():
-    #    yield ('RAMBFIFO36E1', site)
-
     for site in gen_bram18():
         yield ('RAMB18E1', site)
 
@@ -100,6 +92,7 @@ for loci, (site_type, site) in enumerate(brams):
 
         return ('my_RAMB18E1', ports, params)
 
+    '''
     def place_bram36():
         ports = {
             'clk': 'clk',
@@ -121,10 +114,11 @@ for loci, (site_type, site) in enumerate(brams):
             'WRITE_MODE_B': '"WRITE_FIRST"',
         }
         return ('my_RAMB36E1', ports, params)
+    '''
 
     modname, ports, params = {
         'RAMB18E1': place_bram18,
-        'RAMBFIFO36E1': place_bram36,
+        #'RAMBFIFO36E1': place_bram36,
     }[site_type]()
 
     verilog.instance(modname, 'inst_%u' % loci, ports, params=params)

fuzzers/026-bram-data/generate.py

@@ -6,7 +6,7 @@ from prjxray.segmaker import Segmaker
 
 c2i = {'0': 0, '1': 1}
 
-segmk = Segmaker("design.bits", verbose=True)
+segmk = Segmaker("design.bits")
 segmk.set_def_bt('BLOCK_RAM')
 
 print("Loading tags")

fuzzers/026-bram-data/minitest/.gitignore

@@ -0,0 +1 @@
+build

fuzzers/026-bram-data/minitest/runme.tcl

@@ -9,7 +9,7 @@ set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_po
 set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
 
 create_pblock roi
-set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+
 add_cells_to_pblock [get_pblocks roi] [get_cells roi]
 resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 

fuzzers/026-bram-data/top.py

@@ -9,13 +9,12 @@ import sys
 
 
 def gen_bram36():
-    #yield "RAMB36_X%dY%d" % (x, y)
     for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
         ['RAMBFIFO36E1']):
         yield site_name
 
 
-DUTN = 10
+DUTN = len(list(gen_bram36()))
 DIN_N = DUTN * 8
 DOUT_N = DUTN * 8
 

fuzzers/101-bram-config/.gitignore

@@ -1,2 +0,0 @@
-/specimen_[0-9][0-9][0-9]/
-/seg_clbl[lm].segbits

fuzzers/Makefile

@@ -18,6 +18,8 @@ $(eval $(call fuzzer,016-clbnoutmux,005-tilegrid))
 $(eval $(call fuzzer,017-clbprecyinit,005-tilegrid))
 $(eval $(call fuzzer,018-clbram,005-tilegrid))
 $(eval $(call fuzzer,019-ndi1mux,005-tilegrid))
+$(eval $(call fuzzer,025-bram-config,005-tilegrid))
+$(eval $(call fuzzer,026-bram-data,005-tilegrid))
 $(eval $(call fuzzer,050-intpips,005-tilegrid))
 $(eval $(call fuzzer,051-imuxlout,050-intpips))
 $(eval $(call fuzzer,052-clkin,050-intpips))