mirror of https://github.com/openXC7/prjxray.git
Add MMCM bool attributes
Signed-off-by: Mitja Kleider <mitja@kleider.name>
This commit is contained in:
Mitja Kleider
parent
a86fd6ed1a
commit
7f17e85307
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@ -3,20 +3,20 @@
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N := 8
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N := 8
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include ../fuzzer.mk
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include ../fuzzer.mk
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SEGDATAS=$(addsuffix /segdata_cmt_top_r_upper_t.txt,$(SPECIMENS))
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SEGDATAS=$(addsuffix /segdata_cmt_top_r_lower_b.txt,$(SPECIMENS))
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database: build/segbits_cmt_top_r_upper_t.db
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database: build/segbits_cmt_top_r_lower_b.db
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build/segbits_cmt_top_r_upper_t.rdb: $(SPECIMENS_OK)
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build/segbits_cmt_top_r_lower_b.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o build/segbits_cmt_top_r_upper_t.rdb $(SEGDATAS)
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${XRAY_SEGMATCH} -o build/segbits_cmt_top_r_lower_b.rdb $(SEGDATAS)
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build/segbits_cmt_top_r_upper_t.db: build/segbits_cmt_top_r_upper_t.rdb
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build/segbits_cmt_top_r_lower_b.db: build/segbits_cmt_top_r_lower_b.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_cmt_top_r_upper_t.db $(SEGDATAS)
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${XRAY_MASKMERGE} build/mask_cmt_top_r_lower_b.db $(SEGDATAS)
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pushdb:
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pushdb:
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${XRAY_MERGEDB} cmt_top_r_upper_t build/segbits_cmt_top_r_upper_t.db
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${XRAY_MERGEDB} cmt_top_r_lower_b build/segbits_cmt_top_r_lower_b.db
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${XRAY_MERGEDB} mask_cmt_top_r_upper_t build/mask_cmt_top_r_upper_t.db
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${XRAY_MERGEDB} mask_cmt_top_r_lower_b build/mask_cmt_top_r_lower_b.db
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.PHONY: database pushdb
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.PHONY: database pushdb
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@ -0,0 +1,3 @@
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# MMCM
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`MMCME2_ADV` in [UG953](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug953-vivado-7series-libraries.pdf) lists the available attributes.
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@ -6,15 +6,39 @@ from prjxray.segmaker import Segmaker
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from prjxray import verilog
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from prjxray import verilog
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def bus_tags(segmk, ps, site):
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def clkout_tags(segmk, ps, site):
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""" Notes:
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First bit is only active for value 1, for 1-128 in total 14 bits are toggling.
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The relation is not clear yet, multiplication of the value by 2 does not fully correlate.
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"""
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for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
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for param, tagname in [('CLKOUT1_DIVIDE', 'ZCLKOUT1_DIVIDE')]:
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# 1-128 => 0-127 for actual 7 bit value
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# 1-128 => 0-127 for actual 7 bit value
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paramadj = int(ps[param]) - 1
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paramadj = 2 * int(ps[param])
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bitstr = [int(x) for x in "{0:07b}".format(paramadj)[::-1]]
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bitstr = [int(x) for x in "{0:08b}".format(paramadj)[::-1]]
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# FIXME: only bits 0 and 1 resolving
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# FIXME: only bits 0 and 1 resolving
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# for i in range(7):
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for i in range(8):
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for i in range(2):
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# for i in range(2):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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#if i in [0, 3, 5]:
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# mybit = 1 ^ bitstr[i]
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#else:
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mybit = bitstr[i]
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segmk.add_site_tag(site, '%s[%u]' % (param, i), mybit)
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def misc_tags(segmk, ps, site):
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for boolattr in [
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'STARTUP_WAIT',
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"CLKOUT4_CASCADE",
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"CLKFBOUT_USE_FINE_PS",
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"CLKOUT0_USE_FINE_PS",
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"CLKOUT1_USE_FINE_PS",
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"CLKOUT2_USE_FINE_PS",
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"CLKOUT3_USE_FINE_PS",
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#"CLKOUT4_USE_FINE_PS", # several bits are changing, needs investigation
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"CLKOUT5_USE_FINE_PS",
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"CLKOUT6_USE_FINE_PS"
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]:
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segmk.add_site_tag(site, boolattr, ps[boolattr] == '"TRUE"')
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def run():
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def run():
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@ -30,7 +54,8 @@ def run():
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assert j['module'] == 'my_MMCME2_ADV'
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assert j['module'] == 'my_MMCME2_ADV'
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site = verilog.unquote(ps['LOC'])
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site = verilog.unquote(ps['LOC'])
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bus_tags(segmk, ps, site)
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#clkout_tags(segmk, ps, site)
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misc_tags(segmk, ps, site)
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segmk.compile()
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segmk.compile()
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segmk.write()
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segmk.write()
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@ -10,7 +10,7 @@ import json
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def gen_sites():
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def gen_sites():
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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["PLLE2_ADV"])):
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["MMCME2_ADV"])):
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yield site_name
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yield site_name
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@ -37,11 +37,22 @@ for loci, site in enumerate(sites):
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params = {
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params = {
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"CLKOUT1_DIVIDE": random.randint(1, 128),
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"CLKOUT1_DIVIDE": random.randint(1, 128),
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"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT4_CASCADE": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"STARTUP_WAIT": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKFBOUT_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT0_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT1_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT2_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT3_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT4_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT5_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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"CLKOUT6_USE_FINE_PS": random.choice(["\"TRUE\"", "\"FALSE\""]),
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}
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}
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modname = "my_MMCME2_ADV"
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modname = "my_MMCME2_ADV"
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verilog.instance(modname, "inst_%u" % loci, ports, params=params)
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verilog.instance(modname, "inst_%u" % loci, ports, params=params)
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# LOC isn't support
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# LOC isn't supported
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params["LOC"] = verilog.quote(site)
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params["LOC"] = verilog.quote(site)
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j = {'module': modname, 'i': loci, 'params': params}
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j = {'module': modname, 'i': loci, 'params': params}
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@ -67,6 +78,16 @@ module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
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parameter CLKOUT6_DIVIDE = 1;
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parameter CLKOUT6_DIVIDE = 1;
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parameter DIVCLK_DIVIDE = 1;
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parameter DIVCLK_DIVIDE = 1;
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parameter CLKFBOUT_MULT = 5;
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parameter CLKFBOUT_MULT = 5;
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parameter CLKOUT4_CASCADE = "FALSE";
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parameter STARTUP_WAIT = "FALSE";
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parameter CLKFBOUT_USE_FINE_PS = "FALSE";
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parameter CLKOUT0_USE_FINE_PS = "FALSE";
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parameter CLKOUT1_USE_FINE_PS = "FALSE";
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parameter CLKOUT2_USE_FINE_PS = "FALSE";
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parameter CLKOUT3_USE_FINE_PS = "FALSE";
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parameter CLKOUT4_USE_FINE_PS = "FALSE";
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parameter CLKOUT5_USE_FINE_PS = "FALSE";
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parameter CLKOUT6_USE_FINE_PS = "FALSE";
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(* KEEP, DONT_TOUCH *)
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(* KEEP, DONT_TOUCH *)
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MMCME2_ADV #(
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MMCME2_ADV #(
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@ -75,7 +96,17 @@ module my_MMCME2_ADV (input clk, input [7:0] din, output [7:0] dout);
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE)
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.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
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.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
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.STARTUP_WAIT(STARTUP_WAIT),
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.CLKFBOUT_USE_FINE_PS(CLKFBOUT_USE_FINE_PS),
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.CLKOUT0_USE_FINE_PS(CLKOUT0_USE_FINE_PS),
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.CLKOUT1_USE_FINE_PS(CLKOUT1_USE_FINE_PS),
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.CLKOUT2_USE_FINE_PS(CLKOUT2_USE_FINE_PS),
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.CLKOUT3_USE_FINE_PS(CLKOUT3_USE_FINE_PS),
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.CLKOUT4_USE_FINE_PS(CLKOUT4_USE_FINE_PS),
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.CLKOUT5_USE_FINE_PS(CLKOUT5_USE_FINE_PS),
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.CLKOUT6_USE_FINE_PS(CLKOUT6_USE_FINE_PS)
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) dut(
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) dut(
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.CLKFBOUT(),
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.CLKFBOUT(),
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.CLKFBOUTB(),
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.CLKFBOUTB(),
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