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tilegrid: BRAM partial support 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-10-09 19:00:39 -07:00
parent 7053663aa6
commit 7c84e3ccc9
2 changed files with 166 additions and 90 deletions
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213
fuzzers/005-tilegrid/generate.tcl
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@ -1,100 +1,143 @@
create_project -force -part $::env(XRAY_PART) design design proc make_project {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog ../top.v read_verilog ../top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
create_pblock roi create_pblock roi
add_cells_to_pblock [get_pblocks roi] [get_cells roi] add_cells_to_pblock [get_pblocks roi] [get_cells roi]
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0 set_param tcl.collectionResultDisplayLimit 0
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
set selected_luts {}
set lut_index 0
if 0 {
set grid_min_x -1
set grid_max_x -1
set grid_min_y -1
set grid_max_y -1
} {
set grid_min_x $::env(XRAY_ROI_GRID_X1)
set grid_max_x $::env(XRAY_ROI_GRID_X2)
set grid_min_y $::env(XRAY_ROI_GRID_Y1)
set grid_max_y $::env(XRAY_ROI_GRID_Y2)
} }
# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per column) proc loc_luts {} {
# Also, if GRID_MIN/MAX is not defined, automatically create it based on used CLBs set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
# See caveat in README on automatic creation set selected_luts {}
foreach lut $luts { set lut_index 0
set tile [get_tile -of_objects $lut]
set grid_x [get_property GRID_POINT_X $tile]
set grid_y [get_property GRID_POINT_Y $tile]
if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x} # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x} foreach lut $luts {
set tile [get_tile -of_objects $lut]
set grid_x [get_property GRID_POINT_X $tile]
set grid_y [get_property GRID_POINT_Y $tile]
if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y} # 50 per column => 50, 100, 150, etc
if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y} # ex: SLICE_X2Y50/A6LUT
if [regexp "Y.*[05]0/" $lut] {
# 50 per column => 50, 100, 150, etc set cell [get_cells roi/luts[$lut_index].lut]
if [regexp "Y(0|[0-9]*[05]0)/" $lut] { set_property LOC [get_sites -of_objects $lut] $cell
set cell [get_cells roi/is[$lut_index].lut] set lut_index [expr $lut_index + 1]
set_property LOC [get_sites -of_objects $lut] $cell lappend selected_luts $lut
set lut_index [expr $lut_index + 1] }
lappend selected_luts $lut }
} return $selected_luts
} }
place_design proc loc_brams {} {
route_design # XXX: for some reason this doesn't work if there is a cell already there
# but LUTs don't have this issue
set brams [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ RAMBFIFO36E1*}]
set selected_brams {}
set bram_index 0
write_checkpoint -force design.dcp # LOC one BRAM (a "selected_lut") into each BRAM segment configuration column (ie 10 per CMT column)
write_bitstream -force design.bit foreach bram $brams {
set tile [get_tile -of_objects $bram]
set grid_x [get_property GRID_POINT_X $tile]
set grid_y [get_property GRID_POINT_Y $tile]
# Get all tiles in ROI, ie not just the selected LUTs # 10 per column => 10, 20, ,etc
set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"] # ex: RAMB36_X0Y10/RAMBFIFO36E1
if [regexp "Y.*0/" $bram] {
# Write tiles.txt with site metadata set cell [get_cells roi/brams[$bram_index].bram]
set fp [open "tiles.txt" w] set_property LOC [get_sites -of_objects $bram] $cell
foreach tile $tiles { set bram_index [expr $bram_index + 1]
set type [get_property TYPE $tile] lappend selected_brams $bram
set grid_x [get_property GRID_POINT_X $tile] }
set grid_y [get_property GRID_POINT_Y $tile] }
set sites [get_sites -quiet -of_objects $tile] return $selected_brams
set typed_sites {}
if [llength $sites] {
set site_types [get_property SITE_TYPE $sites]
foreach t $site_types s $sites {
lappend typed_sites $t $s
}
}
puts $fp "$type $tile $grid_x $grid_y $typed_sites"
}
close $fp
# Toggle one bit in each selected LUT to generate base addresses
for {set i 0} {$i < $lut_index} {incr i} {
set cell [get_cells roi/is[$i].lut]
set orig_init [get_property INIT $cell]
# Flip a bit by changing MSB 0 => 1
set new_init [regsub "h8" $orig_init "h0"]
set_property INIT $new_init $cell
write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
set_property INIT $orig_init $cell
} }
proc write_tiles_txt {} {
# Get all tiles in ROI, ie not just the selected LUTs
set grid_min_x $::env(XRAY_ROI_GRID_X1)
set grid_max_x $::env(XRAY_ROI_GRID_X2)
set grid_min_y $::env(XRAY_ROI_GRID_Y1)
set grid_max_y $::env(XRAY_ROI_GRID_Y2)
set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
# Write tiles.txt with site metadata
set fp [open "tiles.txt" w]
foreach tile $tiles {
set type [get_property TYPE $tile]
set grid_x [get_property GRID_POINT_X $tile]
set grid_y [get_property GRID_POINT_Y $tile]
set sites [get_sites -quiet -of_objects $tile]
set typed_sites {}
if [llength $sites] {
set site_types [get_property SITE_TYPE $sites]
foreach t $site_types s $sites {
lappend typed_sites $t $s
}
}
puts $fp "$type $tile $grid_x $grid_y $typed_sites"
}
close $fp
}
proc write_clbs { selected_luts } {
# Toggle one bit in each selected LUT to generate base addresses
for {set i 0} {$i < [llength $selected_luts]} {incr i} {
set cell [get_cells roi/luts[$i].lut]
set orig_init [get_property INIT $cell]
# Flip a bit by changing MSB 0 => 1
set new_init [regsub "h8" $orig_init "h0"]
set_property INIT $new_init $cell
write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
set_property INIT $orig_init $cell
}
}
proc write_brams { selected_brams } {
# Toggle one bit in each selected BRAM to generate base addresses
for {set i 0} {$i < [llength $selected_brams]} {incr i} {
set cell [get_cells roi/brams[$i].bram]
set orig_init [get_property INIT_00 $cell]
# Flip a bit by changing MSB 0 => 1
set new_init [regsub "h8" $orig_init "h0"]
set_property INIT_00 $new_init $cell
write_bitstream -force design_[get_sites -of_objects [lindex $selected_brams $i]].bit
set_property INIT_00 $orig_init $cell
}
}
proc run {} {
make_project
set selected_luts [loc_luts]
set selected_brams [loc_brams]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_tiles_txt
write_clbs $selected_luts
write_brams $selected_brams
}
run

43
fuzzers/005-tilegrid/top.v
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@ -1,9 +1,10 @@
//Need at least one LUT per frame base address we want //Need at least one LUT per frame base address we want
`define N 100 `define N_LUT 100
`define N_BRAM 8
module top(input clk, stb, di, output do); module top(input clk, stb, di, output do);
localparam integer DIN_N = 6; localparam integer DIN_N = 8;
localparam integer DOUT_N = `N; localparam integer DOUT_N = `N_LUT + `N_BRAM;
reg [DIN_N-1:0] din; reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout; wire [DOUT_N-1:0] dout;
@ -29,10 +30,10 @@ module top(input clk, stb, di, output do);
); );
endmodule endmodule
module roi(input clk, input [5:0] din, output [`N-1:0] dout); module roi(input clk, input [7:0] din, output [`N_LUT + `N_BRAM-1:0] dout);
genvar i; genvar i;
generate generate
for (i = 0; i < `N; i = i+1) begin:is for (i = 0; i < `N_LUT; i = i+1) begin:luts
LUT6 #( LUT6 #(
.INIT(64'h8000_0000_0000_0001 + (i << 16)) .INIT(64'h8000_0000_0000_0001 + (i << 16))
) lut ( ) lut (
@ -46,4 +47,36 @@ module roi(input clk, input [5:0] din, output [`N-1:0] dout);
); );
end end
endgenerate endgenerate
genvar j;
generate
for (j = 0; j < `N_BRAM; j = j+1) begin:brams
(* KEEP, DONT_TOUCH *)
RAMB36E1 #(
.INIT_00(256'h8000000000000000000000000000000000000000000000000000000000000000 + (j << 16))
) bram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[j + `N_LUT]),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
end
endgenerate
endmodule endmodule