mirror of https://github.com/openXC7/prjxray.git
tilegrid: BRAM partial support
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
7053663aa6
commit
7c84e3ccc9
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@ -1,100 +1,143 @@
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create_project -force -part $::env(XRAY_PART) design design
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proc make_project {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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if 0 {
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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} {
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set grid_min_x $::env(XRAY_ROI_GRID_X1)
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set grid_max_x $::env(XRAY_ROI_GRID_X2)
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set grid_min_y $::env(XRAY_ROI_GRID_Y1)
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set grid_max_y $::env(XRAY_ROI_GRID_Y2)
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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}
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per column)
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# Also, if GRID_MIN/MAX is not defined, automatically create it based on used CLBs
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# See caveat in README on automatic creation
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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proc loc_luts {} {
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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# 50 per column => 50, 100, 150, etc
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if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
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set cell [get_cells roi/is[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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}
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# 50 per column => 50, 100, 150, etc
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# ex: SLICE_X2Y50/A6LUT
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if [regexp "Y.*[05]0/" $lut] {
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set cell [get_cells roi/luts[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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}
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}
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return $selected_luts
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}
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place_design
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route_design
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proc loc_brams {} {
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# XXX: for some reason this doesn't work if there is a cell already there
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# but LUTs don't have this issue
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set brams [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ RAMBFIFO36E1*}]
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set selected_brams {}
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set bram_index 0
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# LOC one BRAM (a "selected_lut") into each BRAM segment configuration column (ie 10 per CMT column)
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foreach bram $brams {
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set tile [get_tile -of_objects $bram]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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# Get all tiles in ROI, ie not just the selected LUTs
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set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
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# Write tiles.txt with site metadata
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set sites [get_sites -quiet -of_objects $tile]
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set typed_sites {}
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if [llength $sites] {
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set site_types [get_property SITE_TYPE $sites]
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foreach t $site_types s $sites {
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lappend typed_sites $t $s
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $typed_sites"
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}
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close $fp
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# Toggle one bit in each selected LUT to generate base addresses
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for {set i 0} {$i < $lut_index} {incr i} {
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set cell [get_cells roi/is[$i].lut]
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set orig_init [get_property INIT $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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set_property INIT $new_init $cell
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write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
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set_property INIT $orig_init $cell
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# 10 per column => 10, 20, ,etc
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# ex: RAMB36_X0Y10/RAMBFIFO36E1
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if [regexp "Y.*0/" $bram] {
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set cell [get_cells roi/brams[$bram_index].bram]
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set_property LOC [get_sites -of_objects $bram] $cell
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set bram_index [expr $bram_index + 1]
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lappend selected_brams $bram
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}
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}
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return $selected_brams
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}
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proc write_tiles_txt {} {
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# Get all tiles in ROI, ie not just the selected LUTs
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set grid_min_x $::env(XRAY_ROI_GRID_X1)
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set grid_max_x $::env(XRAY_ROI_GRID_X2)
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set grid_min_y $::env(XRAY_ROI_GRID_Y1)
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set grid_max_y $::env(XRAY_ROI_GRID_Y2)
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set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
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# Write tiles.txt with site metadata
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set sites [get_sites -quiet -of_objects $tile]
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set typed_sites {}
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if [llength $sites] {
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set site_types [get_property SITE_TYPE $sites]
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foreach t $site_types s $sites {
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lappend typed_sites $t $s
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $typed_sites"
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}
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close $fp
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}
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proc write_clbs { selected_luts } {
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# Toggle one bit in each selected LUT to generate base addresses
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for {set i 0} {$i < [llength $selected_luts]} {incr i} {
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set cell [get_cells roi/luts[$i].lut]
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set orig_init [get_property INIT $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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set_property INIT $new_init $cell
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write_bitstream -force design_[get_sites -of_objects [lindex $selected_luts $i]].bit
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set_property INIT $orig_init $cell
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}
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}
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proc write_brams { selected_brams } {
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# Toggle one bit in each selected BRAM to generate base addresses
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for {set i 0} {$i < [llength $selected_brams]} {incr i} {
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set cell [get_cells roi/brams[$i].bram]
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set orig_init [get_property INIT_00 $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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set_property INIT_00 $new_init $cell
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write_bitstream -force design_[get_sites -of_objects [lindex $selected_brams $i]].bit
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set_property INIT_00 $orig_init $cell
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}
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}
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proc run {} {
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make_project
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set selected_luts [loc_luts]
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set selected_brams [loc_brams]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_tiles_txt
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write_clbs $selected_luts
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write_brams $selected_brams
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}
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run
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@ -1,9 +1,10 @@
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//Need at least one LUT per frame base address we want
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`define N 100
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`define N_LUT 100
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`define N_BRAM 8
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = `N;
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localparam integer DIN_N = 8;
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localparam integer DOUT_N = `N_LUT + `N_BRAM;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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@ -29,10 +30,10 @@ module top(input clk, stb, di, output do);
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);
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endmodule
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module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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module roi(input clk, input [7:0] din, output [`N_LUT + `N_BRAM-1:0] dout);
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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for (i = 0; i < `N_LUT; i = i+1) begin:luts
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 16))
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) lut (
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@ -46,4 +47,36 @@ module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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);
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end
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endgenerate
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genvar j;
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generate
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for (j = 0; j < `N_BRAM; j = j+1) begin:brams
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(* KEEP, DONT_TOUCH *)
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RAMB36E1 #(
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.INIT_00(256'h8000000000000000000000000000000000000000000000000000000000000000 + (j << 16))
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) bram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[j + `N_LUT]),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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end
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endgenerate
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endmodule
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