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Convert BRAM block tilegrid fuzzer to use first RAMB18E1. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-13 18:25:09 -08:00
parent ab7347877f
commit 7c467920e6
2 changed files with 10 additions and 57 deletions
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7
fuzzers/005-tilegrid/bram_block/generate.tcl
View File

@ -5,17 +5,10 @@ proc run {} {
read_verilog top.v read_verilog top.v
synth_design -top top synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design place_design
route_design route_design

60
fuzzers/005-tilegrid/bram_block/top.py
View File

@ -13,7 +13,7 @@ def gen_sites():
gridinfo = grid.gridinfo_at_loc(loc) gridinfo = grid.gridinfo_at_loc(loc)
for site_name, site_type in gridinfo.sites.items(): for site_name, site_type in gridinfo.sites.items():
if site_type in ['RAMBFIFO36E1']: if site_type in ['FIFO18E1']:
yield tile_name, site_name yield tile_name, site_name
@ -25,28 +25,8 @@ def write_params(params):
def run(): def run():
print( print('''
''' module top();
module top(input clk, stb, di, output do);
localparam integer DIN_N = 8;
localparam integer DOUT_N = 8;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
''') ''')
params = {} params = {}
@ -58,33 +38,13 @@ module top(input clk, stb, di, output do);
print( print(
''' '''
(* KEEP, DONT_TOUCH, LOC = "%s" *) (* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
RAMB36E1 #( RAMB18E1 #(
.INIT_00(256'b%u) .INIT_00(256'b{isone})
) bram_%s ( ) bram_{site_name} ();'''.format(
.CLKARDCLK(), site_name=site_name,
.CLKBWRCLK(), isone=isone,
.ENARDEN(), ))
.ENBWREN(),
.REGCEAREGCE(),
.REGCEB(),
.RSTRAMARSTRAM(),
.RSTRAMB(),
.RSTREGARSTREG(),
.RSTREGB(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.DIADI(),
.DIBDI(),
.DIPADIP(),
.DIPBDIP(),
.WEA(),
.WEBWE(),
.DOADO(),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
''' % (site_name, isone, site_name))
print("endmodule") print("endmodule")
write_params(params) write_params(params)