Convert BRAM block tilegrid fuzzer to use first RAMB18E1.

Signed-off-by: Keith Rothman <[email protected]>
This commit is contained in:
Keith Rothman
2019-02-13 18:25:09 -08:00
parent ab7347877f
commit 7c467920e6
2 changed files with 10 additions and 57 deletions
+10 -50
View File
@@ -13,7 +13,7 @@ def gen_sites():
gridinfo = grid.gridinfo_at_loc(loc)
for site_name, site_type in gridinfo.sites.items():
if site_type in ['RAMBFIFO36E1']:
if site_type in ['FIFO18E1']:
yield tile_name, site_name
@@ -25,28 +25,8 @@ def write_params(params):
def run():
print(
'''
module top(input clk, stb, di, output do);
localparam integer DIN_N = 8;
localparam integer DOUT_N = 8;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
print('''
module top();
''')
params = {}
@@ -58,33 +38,13 @@ module top(input clk, stb, di, output do);
print(
'''
(* KEEP, DONT_TOUCH, LOC = "%s" *)
RAMB36E1 #(
.INIT_00(256'b%u)
) bram_%s (
.CLKARDCLK(),
.CLKBWRCLK(),
.ENARDEN(),
.ENBWREN(),
.REGCEAREGCE(),
.REGCEB(),
.RSTRAMARSTRAM(),
.RSTRAMB(),
.RSTREGARSTREG(),
.RSTREGB(),
.ADDRARDADDR(),
.ADDRBWRADDR(),
.DIADI(),
.DIBDI(),
.DIPADIP(),
.DIPBDIP(),
.WEA(),
.WEBWE(),
.DOADO(),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
''' % (site_name, isone, site_name))
(* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
RAMB18E1 #(
.INIT_00(256'b{isone})
) bram_{site_name} ();'''.format(
site_name=site_name,
isone=isone,
))
print("endmodule")
write_params(params)