mirror of https://github.com/openXC7/prjxray.git
clbn5ffmux fuzzer
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
8317c00c4e
commit
7c2500eee7
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@ -0,0 +1,22 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -0,0 +1,16 @@
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Purpose:
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Document A5FFMUX family of CLB muxes
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Algorithm:
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*5FFMUX
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Inputs can come from either the LUT6_2 NO5 output or the CLB NX input
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To perturb the CLB the smallest, want LUT6 always instantiated
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However, some routing congestion that would require putting FFs in bypass
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(which turns out is actually okay, but didn't realize that at the time)
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Decided instead ot instantiate LUT8, but not use the output
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Turns out this is okay and won't optimize things away
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So then, the 5FF D input is switched between the O5 output and an external CLB input
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Outcome:
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Bits are one hot encoded per mux position
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@ -0,0 +1,33 @@
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#!/usr/bin/env python3
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags")
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'''
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module,loc,n,def_a
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clb_N5FFMUX,SLICE_X12Y100,3,1
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clb_N5FFMUX,SLICE_X13Y100,0,1
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clb_N5FFMUX,SLICE_X14Y100,3,1
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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module,loc,n,def_a = l.split(',')
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def_a = int(def_a)
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n = int(n)
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#which = chr(ord('A') + n)
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for i, which in enumerate('ABCD'):
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# Theory: there is one bit for each mux positon
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# In each config 3 muxes are in one position, other 3 are in another
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inv = int(i == n)
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segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
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segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
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segmk.compile()
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segmk.write()
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@ -0,0 +1,17 @@
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,200 @@
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import random
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random.seed(0)
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CLBN = 40
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# SLICE_X12Y100
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# SLICE_X27Y149
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SLICEX = (12, 28)
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SLICEY = (100, 150)
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,n,def_a\n')
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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bel = ''
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module = 'clb_N5FFMUX'
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n = random.randint(0, 3)
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def_a = random.randint(0, 1)
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loc = next(slices)
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print(' %s' % module)
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print(' #(.LOC("%s"), .N(%d), .DEF_A(%d))' % (loc, n, def_a))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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f.write('%s,%s,%s,%s\n' % (module, loc, n, def_a))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X22Y100";
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parameter N=-1;
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parameter DEF_A=1;
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wire lutdo, lutco, lutbo, lutao;
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wire lut7bo, lut7ao;
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wire lut8o;
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reg [3:0] ffds;
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wire lutdo5, lutco5, lutbo5, lutao5;
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//wire lutno5 [3:0] = {lutao5, lutbo5, lutco5, lutdo5};
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wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};
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always @(*) begin
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if (DEF_A) begin
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//Default poliarty A
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ffds[3] = lutdo5;
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ffds[2] = lutco5;
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ffds[1] = lutbo5;
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ffds[0] = lutao5;
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ffds[N] = din[6];
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end else begin
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//Default polarity B
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ffds[3] = din[6];
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ffds[2] = din[6];
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ffds[1] = din[6];
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ffds[0] = din[6];
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ffds[N] = lutno5[N];
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end
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end
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(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
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MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
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(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
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(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
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MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
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(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutdo5),
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.O6(lutdo));
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(* LOC=LOC, BEL="D5FF" *)
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FDPE ffd (
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.C(clk),
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.Q(dout[1]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(ffds[3]));
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(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_BEEF_0000_0001)
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) lutc (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutco5),
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.O6(lutco));
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(* LOC=LOC, BEL="C5FF" *)
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FDPE ffc (
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.C(clk),
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.Q(dout[2]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(ffds[2]));
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(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_CAFE_0000_0001)
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) lutb (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutbo5),
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.O6(lutbo));
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(* LOC=LOC, BEL="B5FF" *)
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FDPE ffb (
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.C(clk),
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.Q(dout[3]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(ffds[1]));
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(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_1CE0_0000_0001)
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) luta (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(lutao5),
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.O6(lutao));
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(* LOC=LOC, BEL="A5FF" *)
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FDPE ffa (
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.C(clk),
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.Q(dout[4]),
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.CE(din[0]),
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.PRE(din[1]),
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//D can only come from O5 or AX
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//AX is used by MUXF7:S
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.D(ffds[0]));
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endmodule
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''')
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