mirror of https://github.com/openXC7/prjxray.git
dbfixup: fix zero enums
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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7acefbb2bb
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@ -122,11 +122,6 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
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line = line.strip()
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line = line.strip()
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if line == llast:
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if line == llast:
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continue
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continue
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# FIXME: quick workaround
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# was in mergedb.sh
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# if re.match(r'.*<m.*>.*', line):
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if re.match(r'.*<.*>.*', line):
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continue
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tag, bits, mode = util.parse_db_line(line)
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tag, bits, mode = util.parse_db_line(line)
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assert mode not in (
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assert mode not in (
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@ -138,7 +133,9 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
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else:
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else:
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if mode:
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if mode:
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assert mode == "<0 candidates>", line
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assert mode == "<0 candidates>", line
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bits = set(bits)
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bits = set()
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else:
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bits = set(bits)
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"""
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"""
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This appears to be a large range of one hot interconnect bits
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This appears to be a large range of one hot interconnect bits
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They are immediately before the first CLB real bits
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They are immediately before the first CLB real bits
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@ -150,6 +147,10 @@ def add_zero_bits(fn_in, fn_out, zero_db, clb_int=False, verbose=False):
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new_line = " ".join([tag] + sorted(bits))
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new_line = " ".join([tag] + sorted(bits))
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if re.match(r'.*<.*>.*', new_line):
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print("Original line: %s" % line)
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assert 0, "Failed to remove line mode: %s" % (new_line)
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if new_line != line:
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if new_line != line:
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changes += 1
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changes += 1
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new_lines.add(new_line)
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new_lines.add(new_line)
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