timfuz: zero row add assertion

Signed-off-by: John McMaster <johndmcmaster@gmail.com>

fuzzers/007-timing/projects/.gitignore

@@ -0,0 +1,3 @@
+specimen_*
+build
+

fuzzers/007-timing/projects/generate.sh

@@ -0,0 +1,9 @@
+#!/bin/bash
+
+source ${XRAY_GENHEADER}
+TIMFUZ_DIR=$XRAY_DIR/fuzzers/007-timing
+
+timing_txt2csv () {
+    python3 $TIMFUZ_DIR/timing_txt2csv.py --speed-json $TIMFUZ_DIR/speed/build/speed.json --out timing3.csv timing3.txt
+}
+

fuzzers/007-timing/projects/oneblinkw/Makefile

@@ -0,0 +1,2 @@
+include ../project.mk
+

fuzzers/007-timing/projects/oneblinkw/generate.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+
+set -ex
+source ../generate.sh
+
+vivado -mode batch -source ../generate.tcl
+timing_txt2csv
+

fuzzers/007-timing/projects/oneblinkw/generate.tcl

@@ -0,0 +1,47 @@
+source ../../../../../utils/utils.tcl
+source ../../project.tcl
+
+proc build_design {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog ../top.v
+    synth_design -top top
+
+    puts "Locking pins"
+    set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
+		[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
+
+    puts "Package stuff"
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+    puts "pblocking"
+    create_pblock roi
+    set roipb [get_pblocks roi]
+    set_property EXCLUDE_PLACEMENT 1 $roipb
+    add_cells_to_pblock $roipb [get_cells roi]
+    resize_pblock $roipb -add "$::env(XRAY_ROI)"
+
+    puts "randplace"
+    #randplace_pblock 50 roi
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    puts "dedicated route"
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    # disable combinitorial loop
+    # set_property IS_ENABLED 0 [get_drc_checks {LUTLP-1}]
+    #write_bitstream -force design.bit
+}
+
+build_design
+write_info3
+

fuzzers/007-timing/projects/oneblinkw/top.v

@@ -0,0 +1,37 @@
+module roi (
+        input wire clk,
+        output wire out);
+    reg [23:0] counter;
+    assign out = counter[23] ^ counter[22] ^ counter[2] && counter[1] || counter[0];
+
+    always @(posedge clk) begin
+        counter <= counter + 1;
+    end
+endmodule
+
+module top(input wire clk, input wire stb, input wire di, output wire do);
+    localparam integer DIN_N = 0;
+    localparam integer DOUT_N = 1;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+    roi roi(
+            .clk(clk),
+            .out(dout[0])
+            );
+endmodule
+

fuzzers/007-timing/timfuz.py

@@ -153,10 +153,10 @@ def simplify_rows(Ads, b_ub, remove_zd=False):
             zero_ds += 1
             continue
 
-        # A very few of these exist with very small values
-        # TODO: investigate, understand what these are
-        # Leaving these in can make the result unsolvable since there does not exist a set of constants to reach the delay
+        # think ran into these before when taking out ZERO elements
         if len(rowd) == 0:
+            if b != 0:
+                assert zero_es == 0, 'Unexpected zero element row with non-zero delay'
             zero_es += 1
             continue